1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NXP (Philips) SCC+++(SCN+++) serial driver
4 *
5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
6 *
7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/device.h>
16 #include <linux/console.h>
17 #include <linux/serial_core.h>
18 #include <linux/serial.h>
19 #include <linux/io.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/serial-sccnxp.h>
25 #include <linux/regulator/consumer.h>
26
27 #define SCCNXP_NAME "uart-sccnxp"
28 #define SCCNXP_MAJOR 204
29 #define SCCNXP_MINOR 205
30
31 #define SCCNXP_MR_REG (0x00)
32 # define MR0_BAUD_NORMAL (0 << 0)
33 # define MR0_BAUD_EXT1 (1 << 0)
34 # define MR0_BAUD_EXT2 (5 << 0)
35 # define MR0_FIFO (1 << 3)
36 # define MR0_TXLVL (1 << 4)
37 # define MR1_BITS_5 (0 << 0)
38 # define MR1_BITS_6 (1 << 0)
39 # define MR1_BITS_7 (2 << 0)
40 # define MR1_BITS_8 (3 << 0)
41 # define MR1_PAR_EVN (0 << 2)
42 # define MR1_PAR_ODD (1 << 2)
43 # define MR1_PAR_NO (4 << 2)
44 # define MR2_STOP1 (7 << 0)
45 # define MR2_STOP2 (0xf << 0)
46 #define SCCNXP_SR_REG (0x01)
47 # define SR_RXRDY (1 << 0)
48 # define SR_FULL (1 << 1)
49 # define SR_TXRDY (1 << 2)
50 # define SR_TXEMT (1 << 3)
51 # define SR_OVR (1 << 4)
52 # define SR_PE (1 << 5)
53 # define SR_FE (1 << 6)
54 # define SR_BRK (1 << 7)
55 #define SCCNXP_CSR_REG (SCCNXP_SR_REG)
56 # define CSR_TIMER_MODE (0x0d)
57 #define SCCNXP_CR_REG (0x02)
58 # define CR_RX_ENABLE (1 << 0)
59 # define CR_RX_DISABLE (1 << 1)
60 # define CR_TX_ENABLE (1 << 2)
61 # define CR_TX_DISABLE (1 << 3)
62 # define CR_CMD_MRPTR1 (0x01 << 4)
63 # define CR_CMD_RX_RESET (0x02 << 4)
64 # define CR_CMD_TX_RESET (0x03 << 4)
65 # define CR_CMD_STATUS_RESET (0x04 << 4)
66 # define CR_CMD_BREAK_RESET (0x05 << 4)
67 # define CR_CMD_START_BREAK (0x06 << 4)
68 # define CR_CMD_STOP_BREAK (0x07 << 4)
69 # define CR_CMD_MRPTR0 (0x0b << 4)
70 #define SCCNXP_RHR_REG (0x03)
71 #define SCCNXP_THR_REG SCCNXP_RHR_REG
72 #define SCCNXP_IPCR_REG (0x04)
73 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
74 # define ACR_BAUD0 (0 << 7)
75 # define ACR_BAUD1 (1 << 7)
76 # define ACR_TIMER_MODE (6 << 4)
77 #define SCCNXP_ISR_REG (0x05)
78 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
79 # define IMR_TXRDY (1 << 0)
80 # define IMR_RXRDY (1 << 1)
81 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
82 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
83 #define SCCNXP_CTPU_REG (0x06)
84 #define SCCNXP_CTPL_REG (0x07)
85 #define SCCNXP_IPR_REG (0x0d)
86 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
87 #define SCCNXP_SOP_REG (0x0e)
88 #define SCCNXP_START_COUNTER_REG SCCNXP_SOP_REG
89 #define SCCNXP_ROP_REG (0x0f)
90
91 /* Route helpers */
92 #define MCTRL_MASK(sig) (0xf << (sig))
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
95
96 #define SCCNXP_HAVE_IO 0x00000001
97 #define SCCNXP_HAVE_MR0 0x00000002
98
99 struct sccnxp_chip {
100 const char *name;
101 unsigned int nr;
102 unsigned long freq_min;
103 unsigned long freq_std;
104 unsigned long freq_max;
105 unsigned int flags;
106 unsigned int fifosize;
107 /* Time between read/write cycles */
108 unsigned int trwd;
109 };
110
111 struct sccnxp_port {
112 struct uart_driver uart;
113 struct uart_port port[SCCNXP_MAX_UARTS];
114 bool opened[SCCNXP_MAX_UARTS];
115
116 int irq;
117 u8 imr;
118
119 struct sccnxp_chip *chip;
120
121 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
122 struct console console;
123 #endif
124
125 spinlock_t lock;
126
127 bool poll;
128 struct timer_list timer;
129
130 struct sccnxp_pdata pdata;
131
132 struct regulator *regulator;
133 };
134
135 static const struct sccnxp_chip sc2681 = {
136 .name = "SC2681",
137 .nr = 2,
138 .freq_min = 1000000,
139 .freq_std = 3686400,
140 .freq_max = 4000000,
141 .flags = SCCNXP_HAVE_IO,
142 .fifosize = 3,
143 .trwd = 200,
144 };
145
146 static const struct sccnxp_chip sc2691 = {
147 .name = "SC2691",
148 .nr = 1,
149 .freq_min = 1000000,
150 .freq_std = 3686400,
151 .freq_max = 4000000,
152 .flags = 0,
153 .fifosize = 3,
154 .trwd = 150,
155 };
156
157 static const struct sccnxp_chip sc2692 = {
158 .name = "SC2692",
159 .nr = 2,
160 .freq_min = 1000000,
161 .freq_std = 3686400,
162 .freq_max = 4000000,
163 .flags = SCCNXP_HAVE_IO,
164 .fifosize = 3,
165 .trwd = 30,
166 };
167
168 static const struct sccnxp_chip sc2891 = {
169 .name = "SC2891",
170 .nr = 1,
171 .freq_min = 100000,
172 .freq_std = 3686400,
173 .freq_max = 8000000,
174 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
175 .fifosize = 16,
176 .trwd = 27,
177 };
178
179 static const struct sccnxp_chip sc2892 = {
180 .name = "SC2892",
181 .nr = 2,
182 .freq_min = 100000,
183 .freq_std = 3686400,
184 .freq_max = 8000000,
185 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
186 .fifosize = 16,
187 .trwd = 17,
188 };
189
190 static const struct sccnxp_chip sc28202 = {
191 .name = "SC28202",
192 .nr = 2,
193 .freq_min = 1000000,
194 .freq_std = 14745600,
195 .freq_max = 50000000,
196 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
197 .fifosize = 256,
198 .trwd = 10,
199 };
200
201 static const struct sccnxp_chip sc68681 = {
202 .name = "SC68681",
203 .nr = 2,
204 .freq_min = 1000000,
205 .freq_std = 3686400,
206 .freq_max = 4000000,
207 .flags = SCCNXP_HAVE_IO,
208 .fifosize = 3,
209 .trwd = 200,
210 };
211
212 static const struct sccnxp_chip sc68692 = {
213 .name = "SC68692",
214 .nr = 2,
215 .freq_min = 1000000,
216 .freq_std = 3686400,
217 .freq_max = 4000000,
218 .flags = SCCNXP_HAVE_IO,
219 .fifosize = 3,
220 .trwd = 200,
221 };
222
sccnxp_read(struct uart_port * port,u8 reg)223 static u8 sccnxp_read(struct uart_port *port, u8 reg)
224 {
225 struct sccnxp_port *s = dev_get_drvdata(port->dev);
226 u8 ret;
227
228 ret = readb(port->membase + (reg << port->regshift));
229
230 ndelay(s->chip->trwd);
231
232 return ret;
233 }
234
sccnxp_write(struct uart_port * port,u8 reg,u8 v)235 static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
236 {
237 struct sccnxp_port *s = dev_get_drvdata(port->dev);
238
239 writeb(v, port->membase + (reg << port->regshift));
240
241 ndelay(s->chip->trwd);
242 }
243
sccnxp_port_read(struct uart_port * port,u8 reg)244 static u8 sccnxp_port_read(struct uart_port *port, u8 reg)
245 {
246 return sccnxp_read(port, (port->line << 3) + reg);
247 }
248
sccnxp_port_write(struct uart_port * port,u8 reg,u8 v)249 static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
250 {
251 sccnxp_write(port, (port->line << 3) + reg, v);
252 }
253
sccnxp_update_best_err(int a,int b,int * besterr)254 static int sccnxp_update_best_err(int a, int b, int *besterr)
255 {
256 int err = abs(a - b);
257
258 if (*besterr > err) {
259 *besterr = err;
260 return 0;
261 }
262
263 return 1;
264 }
265
266 static const struct {
267 u8 csr;
268 u8 acr;
269 u8 mr0;
270 int baud;
271 } baud_std[] = {
272 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
273 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
274 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
275 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
276 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
277 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
278 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
279 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
280 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
281 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
282 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
283 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
284 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
285 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
286 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
287 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
288 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
289 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
290 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
291 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
292 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
293 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
294 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
295 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
296 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
297 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
298 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
299 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
300 { 0, 0, 0, 0 }
301 };
302
sccnxp_set_baud(struct uart_port * port,int baud)303 static int sccnxp_set_baud(struct uart_port *port, int baud)
304 {
305 struct sccnxp_port *s = dev_get_drvdata(port->dev);
306 int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;
307 struct sccnxp_chip *chip = s->chip;
308 u8 i, acr = 0, csr = 0, mr0 = 0;
309
310 /* Find divisor to load to the timer preset registers */
311 div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);
312 if ((div_std >= 2) && (div_std <= 0xffff)) {
313 bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);
314 sccnxp_update_best_err(baud, bestbaud, &besterr);
315 csr = CSR_TIMER_MODE;
316 sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);
317 sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);
318 /* Issue start timer/counter command */
319 sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);
320 }
321
322 /* Find best baud from table */
323 for (i = 0; baud_std[i].baud && besterr; i++) {
324 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
325 continue;
326 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
327 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
328 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
329 acr = baud_std[i].acr;
330 csr = baud_std[i].csr;
331 mr0 = baud_std[i].mr0;
332 bestbaud = tmp_baud;
333 }
334 }
335
336 if (chip->flags & SCCNXP_HAVE_MR0) {
337 /* Enable FIFO, set half level for TX */
338 mr0 |= MR0_FIFO | MR0_TXLVL;
339 /* Update MR0 */
340 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
341 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
342 }
343
344 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
345 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
346
347 if (baud != bestbaud)
348 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
349 baud, bestbaud);
350
351 return bestbaud;
352 }
353
sccnxp_enable_irq(struct uart_port * port,int mask)354 static void sccnxp_enable_irq(struct uart_port *port, int mask)
355 {
356 struct sccnxp_port *s = dev_get_drvdata(port->dev);
357
358 s->imr |= mask << (port->line * 4);
359 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
360 }
361
sccnxp_disable_irq(struct uart_port * port,int mask)362 static void sccnxp_disable_irq(struct uart_port *port, int mask)
363 {
364 struct sccnxp_port *s = dev_get_drvdata(port->dev);
365
366 s->imr &= ~(mask << (port->line * 4));
367 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
368 }
369
sccnxp_set_bit(struct uart_port * port,int sig,int state)370 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
371 {
372 u8 bitmask;
373 struct sccnxp_port *s = dev_get_drvdata(port->dev);
374
375 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
376 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
377 if (state)
378 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
379 else
380 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
381 }
382 }
383
sccnxp_handle_rx(struct uart_port * port)384 static void sccnxp_handle_rx(struct uart_port *port)
385 {
386 u8 sr;
387 unsigned int ch, flag;
388
389 for (;;) {
390 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
391 if (!(sr & SR_RXRDY))
392 break;
393 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
394
395 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
396
397 port->icount.rx++;
398 flag = TTY_NORMAL;
399
400 if (unlikely(sr)) {
401 if (sr & SR_BRK) {
402 port->icount.brk++;
403 sccnxp_port_write(port, SCCNXP_CR_REG,
404 CR_CMD_BREAK_RESET);
405 if (uart_handle_break(port))
406 continue;
407 } else if (sr & SR_PE)
408 port->icount.parity++;
409 else if (sr & SR_FE)
410 port->icount.frame++;
411 else if (sr & SR_OVR) {
412 port->icount.overrun++;
413 sccnxp_port_write(port, SCCNXP_CR_REG,
414 CR_CMD_STATUS_RESET);
415 }
416
417 sr &= port->read_status_mask;
418 if (sr & SR_BRK)
419 flag = TTY_BREAK;
420 else if (sr & SR_PE)
421 flag = TTY_PARITY;
422 else if (sr & SR_FE)
423 flag = TTY_FRAME;
424 else if (sr & SR_OVR)
425 flag = TTY_OVERRUN;
426 }
427
428 if (uart_handle_sysrq_char(port, ch))
429 continue;
430
431 if (sr & port->ignore_status_mask)
432 continue;
433
434 uart_insert_char(port, sr, SR_OVR, ch, flag);
435 }
436
437 tty_flip_buffer_push(&port->state->port);
438 }
439
sccnxp_handle_tx(struct uart_port * port)440 static void sccnxp_handle_tx(struct uart_port *port)
441 {
442 u8 sr;
443 struct circ_buf *xmit = &port->state->xmit;
444 struct sccnxp_port *s = dev_get_drvdata(port->dev);
445
446 if (unlikely(port->x_char)) {
447 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
448 port->icount.tx++;
449 port->x_char = 0;
450 return;
451 }
452
453 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
454 /* Disable TX if FIFO is empty */
455 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
456 sccnxp_disable_irq(port, IMR_TXRDY);
457
458 /* Set direction to input */
459 if (s->chip->flags & SCCNXP_HAVE_IO)
460 sccnxp_set_bit(port, DIR_OP, 0);
461 }
462 return;
463 }
464
465 while (!uart_circ_empty(xmit)) {
466 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
467 if (!(sr & SR_TXRDY))
468 break;
469
470 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
471 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
472 port->icount.tx++;
473 }
474
475 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
476 uart_write_wakeup(port);
477 }
478
sccnxp_handle_events(struct sccnxp_port * s)479 static void sccnxp_handle_events(struct sccnxp_port *s)
480 {
481 int i;
482 u8 isr;
483
484 do {
485 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
486 isr &= s->imr;
487 if (!isr)
488 break;
489
490 for (i = 0; i < s->uart.nr; i++) {
491 if (s->opened[i] && (isr & ISR_RXRDY(i)))
492 sccnxp_handle_rx(&s->port[i]);
493 if (s->opened[i] && (isr & ISR_TXRDY(i)))
494 sccnxp_handle_tx(&s->port[i]);
495 }
496 } while (1);
497 }
498
sccnxp_timer(struct timer_list * t)499 static void sccnxp_timer(struct timer_list *t)
500 {
501 struct sccnxp_port *s = from_timer(s, t, timer);
502 unsigned long flags;
503
504 spin_lock_irqsave(&s->lock, flags);
505 sccnxp_handle_events(s);
506 spin_unlock_irqrestore(&s->lock, flags);
507
508 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
509 }
510
sccnxp_ist(int irq,void * dev_id)511 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
512 {
513 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
514 unsigned long flags;
515
516 spin_lock_irqsave(&s->lock, flags);
517 sccnxp_handle_events(s);
518 spin_unlock_irqrestore(&s->lock, flags);
519
520 return IRQ_HANDLED;
521 }
522
sccnxp_start_tx(struct uart_port * port)523 static void sccnxp_start_tx(struct uart_port *port)
524 {
525 struct sccnxp_port *s = dev_get_drvdata(port->dev);
526 unsigned long flags;
527
528 spin_lock_irqsave(&s->lock, flags);
529
530 /* Set direction to output */
531 if (s->chip->flags & SCCNXP_HAVE_IO)
532 sccnxp_set_bit(port, DIR_OP, 1);
533
534 sccnxp_enable_irq(port, IMR_TXRDY);
535
536 spin_unlock_irqrestore(&s->lock, flags);
537 }
538
sccnxp_stop_tx(struct uart_port * port)539 static void sccnxp_stop_tx(struct uart_port *port)
540 {
541 /* Do nothing */
542 }
543
sccnxp_stop_rx(struct uart_port * port)544 static void sccnxp_stop_rx(struct uart_port *port)
545 {
546 struct sccnxp_port *s = dev_get_drvdata(port->dev);
547 unsigned long flags;
548
549 spin_lock_irqsave(&s->lock, flags);
550 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
551 spin_unlock_irqrestore(&s->lock, flags);
552 }
553
sccnxp_tx_empty(struct uart_port * port)554 static unsigned int sccnxp_tx_empty(struct uart_port *port)
555 {
556 u8 val;
557 unsigned long flags;
558 struct sccnxp_port *s = dev_get_drvdata(port->dev);
559
560 spin_lock_irqsave(&s->lock, flags);
561 val = sccnxp_port_read(port, SCCNXP_SR_REG);
562 spin_unlock_irqrestore(&s->lock, flags);
563
564 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
565 }
566
sccnxp_set_mctrl(struct uart_port * port,unsigned int mctrl)567 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
568 {
569 struct sccnxp_port *s = dev_get_drvdata(port->dev);
570 unsigned long flags;
571
572 if (!(s->chip->flags & SCCNXP_HAVE_IO))
573 return;
574
575 spin_lock_irqsave(&s->lock, flags);
576
577 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
578 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
579
580 spin_unlock_irqrestore(&s->lock, flags);
581 }
582
sccnxp_get_mctrl(struct uart_port * port)583 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
584 {
585 u8 bitmask, ipr;
586 unsigned long flags;
587 struct sccnxp_port *s = dev_get_drvdata(port->dev);
588 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
589
590 if (!(s->chip->flags & SCCNXP_HAVE_IO))
591 return mctrl;
592
593 spin_lock_irqsave(&s->lock, flags);
594
595 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
596
597 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
598 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
599 DSR_IP);
600 mctrl &= ~TIOCM_DSR;
601 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
602 }
603 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
604 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
605 CTS_IP);
606 mctrl &= ~TIOCM_CTS;
607 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
608 }
609 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
610 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
611 DCD_IP);
612 mctrl &= ~TIOCM_CAR;
613 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
614 }
615 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
616 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
617 RNG_IP);
618 mctrl &= ~TIOCM_RNG;
619 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
620 }
621
622 spin_unlock_irqrestore(&s->lock, flags);
623
624 return mctrl;
625 }
626
sccnxp_break_ctl(struct uart_port * port,int break_state)627 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
628 {
629 struct sccnxp_port *s = dev_get_drvdata(port->dev);
630 unsigned long flags;
631
632 spin_lock_irqsave(&s->lock, flags);
633 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
634 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
635 spin_unlock_irqrestore(&s->lock, flags);
636 }
637
sccnxp_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)638 static void sccnxp_set_termios(struct uart_port *port,
639 struct ktermios *termios,
640 const struct ktermios *old)
641 {
642 struct sccnxp_port *s = dev_get_drvdata(port->dev);
643 unsigned long flags;
644 u8 mr1, mr2;
645 int baud;
646
647 spin_lock_irqsave(&s->lock, flags);
648
649 /* Mask termios capabilities we don't support */
650 termios->c_cflag &= ~CMSPAR;
651
652 /* Disable RX & TX, reset break condition, status and FIFOs */
653 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
654 CR_RX_DISABLE | CR_TX_DISABLE);
655 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
657 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
658
659 /* Word size */
660 switch (termios->c_cflag & CSIZE) {
661 case CS5:
662 mr1 = MR1_BITS_5;
663 break;
664 case CS6:
665 mr1 = MR1_BITS_6;
666 break;
667 case CS7:
668 mr1 = MR1_BITS_7;
669 break;
670 case CS8:
671 default:
672 mr1 = MR1_BITS_8;
673 break;
674 }
675
676 /* Parity */
677 if (termios->c_cflag & PARENB) {
678 if (termios->c_cflag & PARODD)
679 mr1 |= MR1_PAR_ODD;
680 } else
681 mr1 |= MR1_PAR_NO;
682
683 /* Stop bits */
684 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
685
686 /* Update desired format */
687 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
688 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
689 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
690
691 /* Set read status mask */
692 port->read_status_mask = SR_OVR;
693 if (termios->c_iflag & INPCK)
694 port->read_status_mask |= SR_PE | SR_FE;
695 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
696 port->read_status_mask |= SR_BRK;
697
698 /* Set status ignore mask */
699 port->ignore_status_mask = 0;
700 if (termios->c_iflag & IGNBRK)
701 port->ignore_status_mask |= SR_BRK;
702 if (termios->c_iflag & IGNPAR)
703 port->ignore_status_mask |= SR_PE;
704 if (!(termios->c_cflag & CREAD))
705 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
706
707 /* Setup baudrate */
708 baud = uart_get_baud_rate(port, termios, old, 50,
709 (s->chip->flags & SCCNXP_HAVE_MR0) ?
710 230400 : 38400);
711 baud = sccnxp_set_baud(port, baud);
712
713 /* Update timeout according to new baud rate */
714 uart_update_timeout(port, termios->c_cflag, baud);
715
716 /* Report actual baudrate back to core */
717 if (tty_termios_baud_rate(termios))
718 tty_termios_encode_baud_rate(termios, baud, baud);
719
720 /* Enable RX & TX */
721 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
722
723 spin_unlock_irqrestore(&s->lock, flags);
724 }
725
sccnxp_startup(struct uart_port * port)726 static int sccnxp_startup(struct uart_port *port)
727 {
728 struct sccnxp_port *s = dev_get_drvdata(port->dev);
729 unsigned long flags;
730
731 spin_lock_irqsave(&s->lock, flags);
732
733 if (s->chip->flags & SCCNXP_HAVE_IO) {
734 /* Outputs are controlled manually */
735 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
736 }
737
738 /* Reset break condition, status and FIFOs */
739 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
740 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
741 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
742 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
743
744 /* Enable RX & TX */
745 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
746
747 /* Enable RX interrupt */
748 sccnxp_enable_irq(port, IMR_RXRDY);
749
750 s->opened[port->line] = 1;
751
752 spin_unlock_irqrestore(&s->lock, flags);
753
754 return 0;
755 }
756
sccnxp_shutdown(struct uart_port * port)757 static void sccnxp_shutdown(struct uart_port *port)
758 {
759 struct sccnxp_port *s = dev_get_drvdata(port->dev);
760 unsigned long flags;
761
762 spin_lock_irqsave(&s->lock, flags);
763
764 s->opened[port->line] = 0;
765
766 /* Disable interrupts */
767 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
768
769 /* Disable TX & RX */
770 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
771
772 /* Leave direction to input */
773 if (s->chip->flags & SCCNXP_HAVE_IO)
774 sccnxp_set_bit(port, DIR_OP, 0);
775
776 spin_unlock_irqrestore(&s->lock, flags);
777 }
778
sccnxp_type(struct uart_port * port)779 static const char *sccnxp_type(struct uart_port *port)
780 {
781 struct sccnxp_port *s = dev_get_drvdata(port->dev);
782
783 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
784 }
785
sccnxp_release_port(struct uart_port * port)786 static void sccnxp_release_port(struct uart_port *port)
787 {
788 /* Do nothing */
789 }
790
sccnxp_request_port(struct uart_port * port)791 static int sccnxp_request_port(struct uart_port *port)
792 {
793 /* Do nothing */
794 return 0;
795 }
796
sccnxp_config_port(struct uart_port * port,int flags)797 static void sccnxp_config_port(struct uart_port *port, int flags)
798 {
799 if (flags & UART_CONFIG_TYPE)
800 port->type = PORT_SC26XX;
801 }
802
sccnxp_verify_port(struct uart_port * port,struct serial_struct * s)803 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
804 {
805 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
806 return 0;
807 if (s->irq == port->irq)
808 return 0;
809
810 return -EINVAL;
811 }
812
813 static const struct uart_ops sccnxp_ops = {
814 .tx_empty = sccnxp_tx_empty,
815 .set_mctrl = sccnxp_set_mctrl,
816 .get_mctrl = sccnxp_get_mctrl,
817 .stop_tx = sccnxp_stop_tx,
818 .start_tx = sccnxp_start_tx,
819 .stop_rx = sccnxp_stop_rx,
820 .break_ctl = sccnxp_break_ctl,
821 .startup = sccnxp_startup,
822 .shutdown = sccnxp_shutdown,
823 .set_termios = sccnxp_set_termios,
824 .type = sccnxp_type,
825 .release_port = sccnxp_release_port,
826 .request_port = sccnxp_request_port,
827 .config_port = sccnxp_config_port,
828 .verify_port = sccnxp_verify_port,
829 };
830
831 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
sccnxp_console_putchar(struct uart_port * port,unsigned char c)832 static void sccnxp_console_putchar(struct uart_port *port, unsigned char c)
833 {
834 int tryes = 100000;
835
836 while (tryes--) {
837 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
838 sccnxp_port_write(port, SCCNXP_THR_REG, c);
839 break;
840 }
841 barrier();
842 }
843 }
844
sccnxp_console_write(struct console * co,const char * c,unsigned n)845 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
846 {
847 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
848 struct uart_port *port = &s->port[co->index];
849 unsigned long flags;
850
851 spin_lock_irqsave(&s->lock, flags);
852 uart_console_write(port, c, n, sccnxp_console_putchar);
853 spin_unlock_irqrestore(&s->lock, flags);
854 }
855
sccnxp_console_setup(struct console * co,char * options)856 static int sccnxp_console_setup(struct console *co, char *options)
857 {
858 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
859 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
860 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
861
862 if (options)
863 uart_parse_options(options, &baud, &parity, &bits, &flow);
864
865 return uart_set_options(port, co, baud, parity, bits, flow);
866 }
867 #endif
868
869 static const struct platform_device_id sccnxp_id_table[] = {
870 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
871 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
872 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
873 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
874 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
875 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
876 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
877 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
878 { }
879 };
880 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
881
sccnxp_probe(struct platform_device * pdev)882 static int sccnxp_probe(struct platform_device *pdev)
883 {
884 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
885 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
886 int i, ret, uartclk;
887 struct sccnxp_port *s;
888 void __iomem *membase;
889 struct clk *clk;
890
891 membase = devm_ioremap_resource(&pdev->dev, res);
892 if (IS_ERR(membase))
893 return PTR_ERR(membase);
894
895 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
896 if (!s) {
897 dev_err(&pdev->dev, "Error allocating port structure\n");
898 return -ENOMEM;
899 }
900 platform_set_drvdata(pdev, s);
901
902 spin_lock_init(&s->lock);
903
904 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
905
906 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
907 if (!IS_ERR(s->regulator)) {
908 ret = regulator_enable(s->regulator);
909 if (ret) {
910 dev_err(&pdev->dev,
911 "Failed to enable regulator: %i\n", ret);
912 return ret;
913 }
914 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
915 return -EPROBE_DEFER;
916
917 clk = devm_clk_get(&pdev->dev, NULL);
918 if (IS_ERR(clk)) {
919 ret = PTR_ERR(clk);
920 if (ret == -EPROBE_DEFER)
921 goto err_out;
922 uartclk = 0;
923 } else {
924 ret = clk_prepare_enable(clk);
925 if (ret)
926 goto err_out;
927
928 ret = devm_add_action_or_reset(&pdev->dev,
929 (void(*)(void *))clk_disable_unprepare,
930 clk);
931 if (ret)
932 goto err_out;
933
934 uartclk = clk_get_rate(clk);
935 }
936
937 if (!uartclk) {
938 dev_notice(&pdev->dev, "Using default clock frequency\n");
939 uartclk = s->chip->freq_std;
940 }
941
942 /* Check input frequency */
943 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
944 dev_err(&pdev->dev, "Frequency out of bounds\n");
945 ret = -EINVAL;
946 goto err_out;
947 }
948
949 if (pdata)
950 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
951
952 if (s->pdata.poll_time_us) {
953 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
954 s->pdata.poll_time_us);
955 s->poll = 1;
956 }
957
958 if (!s->poll) {
959 s->irq = platform_get_irq(pdev, 0);
960 if (s->irq < 0) {
961 ret = -ENXIO;
962 goto err_out;
963 }
964 }
965
966 s->uart.owner = THIS_MODULE;
967 s->uart.dev_name = "ttySC";
968 s->uart.major = SCCNXP_MAJOR;
969 s->uart.minor = SCCNXP_MINOR;
970 s->uart.nr = s->chip->nr;
971 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
972 s->uart.cons = &s->console;
973 s->uart.cons->device = uart_console_device;
974 s->uart.cons->write = sccnxp_console_write;
975 s->uart.cons->setup = sccnxp_console_setup;
976 s->uart.cons->flags = CON_PRINTBUFFER;
977 s->uart.cons->index = -1;
978 s->uart.cons->data = s;
979 strcpy(s->uart.cons->name, "ttySC");
980 #endif
981 ret = uart_register_driver(&s->uart);
982 if (ret) {
983 dev_err(&pdev->dev, "Registering UART driver failed\n");
984 goto err_out;
985 }
986
987 for (i = 0; i < s->uart.nr; i++) {
988 s->port[i].line = i;
989 s->port[i].dev = &pdev->dev;
990 s->port[i].irq = s->irq;
991 s->port[i].type = PORT_SC26XX;
992 s->port[i].fifosize = s->chip->fifosize;
993 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
994 s->port[i].iotype = UPIO_MEM;
995 s->port[i].mapbase = res->start;
996 s->port[i].membase = membase;
997 s->port[i].regshift = s->pdata.reg_shift;
998 s->port[i].uartclk = uartclk;
999 s->port[i].ops = &sccnxp_ops;
1000 s->port[i].has_sysrq = IS_ENABLED(CONFIG_SERIAL_SCCNXP_CONSOLE);
1001 uart_add_one_port(&s->uart, &s->port[i]);
1002 /* Set direction to input */
1003 if (s->chip->flags & SCCNXP_HAVE_IO)
1004 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
1005 }
1006
1007 /* Disable interrupts */
1008 s->imr = 0;
1009 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
1010
1011 if (!s->poll) {
1012 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
1013 sccnxp_ist,
1014 IRQF_TRIGGER_FALLING |
1015 IRQF_ONESHOT,
1016 dev_name(&pdev->dev), s);
1017 if (!ret)
1018 return 0;
1019
1020 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
1021 } else {
1022 timer_setup(&s->timer, sccnxp_timer, 0);
1023 mod_timer(&s->timer, jiffies +
1024 usecs_to_jiffies(s->pdata.poll_time_us));
1025 return 0;
1026 }
1027
1028 uart_unregister_driver(&s->uart);
1029 err_out:
1030 if (!IS_ERR(s->regulator))
1031 regulator_disable(s->regulator);
1032
1033 return ret;
1034 }
1035
sccnxp_remove(struct platform_device * pdev)1036 static int sccnxp_remove(struct platform_device *pdev)
1037 {
1038 int i;
1039 struct sccnxp_port *s = platform_get_drvdata(pdev);
1040
1041 if (!s->poll)
1042 devm_free_irq(&pdev->dev, s->irq, s);
1043 else
1044 del_timer_sync(&s->timer);
1045
1046 for (i = 0; i < s->uart.nr; i++)
1047 uart_remove_one_port(&s->uart, &s->port[i]);
1048
1049 uart_unregister_driver(&s->uart);
1050
1051 if (!IS_ERR(s->regulator))
1052 return regulator_disable(s->regulator);
1053
1054 return 0;
1055 }
1056
1057 static struct platform_driver sccnxp_uart_driver = {
1058 .driver = {
1059 .name = SCCNXP_NAME,
1060 },
1061 .probe = sccnxp_probe,
1062 .remove = sccnxp_remove,
1063 .id_table = sccnxp_id_table,
1064 };
1065 module_platform_driver(sccnxp_uart_driver);
1066
1067 MODULE_LICENSE("GPL v2");
1068 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1069 MODULE_DESCRIPTION("SCCNXP serial driver");
1070
