Searched refs:SPRITE_YUV_ORDER_MASK (Results 1 – 2 of 2) sorted by relevance
431 yuv_order = (val & SPRITE_YUV_ORDER_MASK) >> in intel_vgpu_decode_sprite_plane()
4475 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) macro4476 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)4477 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)4478 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)4479 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
