SOC15_REG_OFFSET (reference) in projects: Linux-v6.1

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Searched refs:SOC15_REG_OFFSET (Results 1 – 25 of 83) sorted by relevance

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/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
D	vce_v4_0.c	67 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr() 69 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); in vce_v4_0_ring_get_rptr() 71 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); in vce_v4_0_ring_get_rptr() 89 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr() 91 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr() 93 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); in vce_v4_0_ring_get_wptr() 115 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), in vce_v4_0_ring_set_wptr() 118 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), in vce_v4_0_ring_set_wptr() 121 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), in vce_v4_0_ring_set_wptr() 132 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded() [all …]
D	jpeg_v1_0.c	41 …ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACK… in jpeg_v1_0_decode_ring_patch_wreg() 60 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); in jpeg_v1_0_decode_ring_set_patch_ring() 66 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); in jpeg_v1_0_decode_ring_set_patch_ring() 78 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring() 84 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA); in jpeg_v1_0_decode_ring_set_patch_ring() 90 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring() 95 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_… in jpeg_v1_0_decode_ring_set_patch_ring() 97 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0… in jpeg_v1_0_decode_ring_set_patch_ring() 99 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ… in jpeg_v1_0_decode_ring_set_patch_ring() 117 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_set_patch_ring() [all …]
D	nbio_v7_2.c	112 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); in nbio_v7_2_sdma_doorbell_range() 134 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); in nbio_v7_2_vcn_doorbell_range() 192 u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE)); in nbio_v7_2_ih_doorbell_range() 207 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE), in nbio_v7_2_ih_doorbell_range() 239 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL)); in nbio_v7_2_update_medium_grain_clock_gating() 257 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data); in nbio_v7_2_update_medium_grain_clock_gating() 269 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); in nbio_v7_2_update_medium_grain_light_sleep() 276 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); in nbio_v7_2_update_medium_grain_light_sleep() 278 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, in nbio_v7_2_update_medium_grain_light_sleep() 288 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1), in nbio_v7_2_update_medium_grain_light_sleep() [all …]
D	umc_v6_1.c	48 rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0, in umc_v6_1_enable_umc_index_mode() 63 rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0, in umc_v6_1_disable_umc_index_mode() 78 rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0, in umc_v6_1_get_umc_index_mode_state() 103 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel() 106 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel() 111 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel() 114 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel() 181 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel_ARCT); in umc_v6_1_query_correctable_error_count() 183 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt_ARCT); in umc_v6_1_query_correctable_error_count() 185 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0_ARCT); in umc_v6_1_query_correctable_error_count() [all …]
D	amdgpu_amdkfd_gfx_v11.c	85 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_CONFIG), sh_mem_config); in program_sh_mem_settings_v11() 86 WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v11() 99 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid, value); in set_pasid_vmid_mapping_v11() 132 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 136 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset() 185 value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS)); in hqd_load_v11() 188 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value); in hqd_load_v11() 193 hqd_base = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_load_v11() 196 reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v11() 203 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data); in hqd_load_v11() [all …]
D	uvd_v7_0.c	549 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 554 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 559 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 565 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 569 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init() 818 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start() 822 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start() 825 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start() 828 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start() 831 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in uvd_v7_0_sriov_start() [all …]
D	amdgpu_amdkfd_gfx_v10_3.c	103 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value); in set_pasid_vmid_mapping_v10_3() 141 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 145 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 149 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 153 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 208 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_load_v10_3() 211 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v10_3() 262 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), in hqd_load_v10_3() 345 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_dump_v10_3() 346 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_dump_v10_3() [all …]
D	amdgpu_amdkfd_gfx_v9.c	93 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings() 94 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings() 119 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping() 122 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping() 128 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping() 133 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping() 136 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping() 139 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping() 145 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping() 150 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping() [all …]
D	vega10_ih.c	53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset() 54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega10_ih_init_register_offset() 55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset() 56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset() 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset() 58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega10_ih_init_register_offset() 59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega10_ih_init_register_offset() 60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega10_ih_init_register_offset() 66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega10_ih_init_register_offset() 67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in vega10_ih_init_register_offset() [all …]
D	mxgpu_ai.c	58 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg() 68 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg() 140 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg() 144 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg() 146 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg() 148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg() 150 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg() 182 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests() 243 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq() 247 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq() [all …]
D	psp_v3_1.c	101 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sysdrv() 119 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sysdrv() 140 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sos() 157 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v3_1_bootloader_load_sos() 204 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_reroute_ih() 216 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_reroute_ih() 254 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, in psp_v3_1_ring_create() 277 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, in psp_v3_1_ring_create() 304 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v3_1_ring_stop() 307 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_ring_stop() [all …]
D	vega20_ih.c	56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset() 57 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega20_ih_init_register_offset() 58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset() 59 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset() 60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset() 61 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega20_ih_init_register_offset() 62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega20_ih_init_register_offset() 63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega20_ih_init_register_offset() 69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega20_ih_init_register_offset() 70 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in vega20_ih_init_register_offset() [all …]
D	navi10_ih.c	55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset() 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in navi10_ih_init_register_offset() 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset() 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset() 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset() 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in navi10_ih_init_register_offset() 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in navi10_ih_init_register_offset() 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in navi10_ih_init_register_offset() 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in navi10_ih_init_register_offset() 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in navi10_ih_init_register_offset() [all …]
D	psp_v12_0.c	145 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sysdrv() 163 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sysdrv() 184 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sos() 201 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v12_0_bootloader_load_sos() 223 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_reroute_ih() 235 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_reroute_ih() 291 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_create() 313 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_ring_create() 339 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_stop() 342 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_ring_stop() [all …]
D	amdgpu_amdkfd_gfx_v10.c	108 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid); in kgd_set_pasid_vmid_mapping() 109 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, in kgd_set_pasid_vmid_mapping() 114 while (!(RREG32(SOC15_REG_OFFSET( in kgd_set_pasid_vmid_mapping() 121 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_set_pasid_vmid_mapping() 128 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_set_pasid_vmid_mapping() 162 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 170 SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset() 186 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - 221 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load() 224 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load() [all …]
D	hdp_v4_0.c	58 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v4_0_invalidate_hdp() 98 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_update_clock_gating() 106 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in hdp_v4_0_update_clock_gating() 108 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in hdp_v4_0_update_clock_gating() 122 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in hdp_v4_0_update_clock_gating() 132 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_get_clockgating_state()
D	amdgpu_amdkfd_arcturus.c	79 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset() 83 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset() 87 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0, in get_sdma_rlc_reg_offset() 91 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0, in get_sdma_rlc_reg_offset() 95 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0, in get_sdma_rlc_reg_offset() 99 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0, in get_sdma_rlc_reg_offset() 103 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0, in get_sdma_rlc_reg_offset() 107 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0, in get_sdma_rlc_reg_offset()
D	vcn_v2_5.c	173 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init() 175 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init() 177 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init() 179 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init() 181 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init() 780 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode() 882 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode() 911 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode() 935 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start() 953 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start() [all …]
D	vcn_v2_0.c	146 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v2_0_sw_init() 148 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_0_sw_init() 150 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_0_sw_init() 152 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_0_sw_init() 154 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v2_0_sw_init() 895 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode() 924 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode() 953 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), in vcn_v2_0_start() 957 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v2_0_start() 997 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start() [all …]
D	umc_v6_7.c	81 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0); in umc_v6_7_query_error_status_helper() 88 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0); in umc_v6_7_query_error_status_helper() 95 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0); in umc_v6_7_query_error_status_helper() 287 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel); in umc_v6_7_query_correctable_error_count() 289 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt); in umc_v6_7_query_correctable_error_count() 291 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_query_correctable_error_count() 329 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v6_7_query_correctable_error_count() 358 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_querry_uncorrectable_error_count() 381 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel() 384 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel() [all …]
D	nbio_v7_0.c	71 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : in nbio_v7_0_sdma_doorbell_range() 72 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); in nbio_v7_0_sdma_doorbell_range() 88 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); in nbio_v7_0_vcn_doorbell_range() 241 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); in nbio_v7_0_get_hdp_flush_req_offset() 246 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); in nbio_v7_0_get_hdp_flush_done_offset() 251 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v7_0_get_pcie_index_offset() 256 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v7_0_get_pcie_data_offset() 278 SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2; in nbio_v7_0_init_registers()
D	vcn_v1_0.c	129 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v1_0_sw_init() 131 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v1_0_sw_init() 133 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v1_0_sw_init() 135 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v1_0_sw_init() 137 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v1_0_sw_init() 805 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start_spg_mode() 854 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode() 858 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_start_spg_mode() 880 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start_spg_mode() 884 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode() [all …]
D	umc_v8_10.c	75 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); in umc_v8_10_clear_error_count_per_channel() 109 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_correctable_error_count() 127 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_uncorrectable_error_count() 217 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_10_query_error_address() 240 mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_10_query_error_address() 302 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel); in umc_v8_10_err_cnt_init_per_channel() 304 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt); in umc_v8_10_err_cnt_init_per_channel() 340 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccCtrl); in umc_v8_10_query_ras_poison_mode_per_channel()
D	nbio_v7_7.c	69 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE); in nbio_v7_7_sdma_doorbell_range() 91 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); in nbio_v7_7_vcn_doorbell_range() 194 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); in nbio_v7_7_get_hdp_flush_req_offset() 199 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); in nbio_v7_7_get_hdp_flush_done_offset() 204 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); in nbio_v7_7_get_pcie_index_offset() 209 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); in nbio_v7_7_get_pcie_data_offset() 214 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); in nbio_v7_7_get_pcie_port_index_offset() 219 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); in nbio_v7_7_get_pcie_port_data_offset()
D	umc_v8_7.c	187 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_clear_error_count_per_channel() 189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_clear_error_count_per_channel() 245 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_query_correctable_error_count() 247 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_query_correctable_error_count() 249 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_correctable_error_count() 288 mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_querry_uncorrectable_error_count() 336 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v8_7_query_error_address() 338 SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v8_7_query_error_address() 397 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCntSel); in umc_v8_7_err_cnt_init_per_channel() 399 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_GeccErrCnt); in umc_v8_7_err_cnt_init_per_channel()

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