1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V13_0_H__ 24 #define __SMU_V13_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04 30 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08 31 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07 32 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04 33 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0_10 0x32 34 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x35 35 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_10 0x1D 36 37 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms 38 39 /* MP Apertures */ 40 #define MP0_Public 0x03800000 41 #define MP0_SRAM 0x03900000 42 #define MP1_Public 0x03b00000 43 #define MP1_SRAM 0x03c00004 44 45 /* address block */ 46 #define smnMP1_FIRMWARE_FLAGS 0x3010024 47 #define smnMP1_V13_0_4_FIRMWARE_FLAGS 0x3010028 48 #define smnMP0_FW_INTF 0x30101c0 49 #define smnMP1_PUB_CTRL 0x3010b14 50 51 #define TEMP_RANGE_MIN (0) 52 #define TEMP_RANGE_MAX (80 * 1000) 53 54 #define SMU13_TOOL_SIZE 0x19000 55 56 #define MAX_DPM_LEVELS 16 57 #define MAX_PCIE_CONF 3 58 59 #define CTF_OFFSET_EDGE 5 60 #define CTF_OFFSET_HOTSPOT 5 61 #define CTF_OFFSET_MEM 5 62 63 struct smu_13_0_max_sustainable_clocks { 64 uint32_t display_clock; 65 uint32_t phy_clock; 66 uint32_t pixel_clock; 67 uint32_t uclock; 68 uint32_t dcef_clock; 69 uint32_t soc_clock; 70 }; 71 72 struct smu_13_0_dpm_clk_level { 73 bool enabled; 74 uint32_t value; 75 }; 76 77 struct smu_13_0_dpm_table { 78 uint32_t min; /* MHz */ 79 uint32_t max; /* MHz */ 80 uint32_t count; 81 bool is_fine_grained; 82 struct smu_13_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 83 }; 84 85 struct smu_13_0_pcie_table { 86 uint8_t pcie_gen[MAX_PCIE_CONF]; 87 uint8_t pcie_lane[MAX_PCIE_CONF]; 88 uint16_t clk_freq[MAX_PCIE_CONF]; 89 uint32_t num_of_link_levels; 90 }; 91 92 struct smu_13_0_dpm_tables { 93 struct smu_13_0_dpm_table soc_table; 94 struct smu_13_0_dpm_table gfx_table; 95 struct smu_13_0_dpm_table uclk_table; 96 struct smu_13_0_dpm_table eclk_table; 97 struct smu_13_0_dpm_table vclk_table; 98 struct smu_13_0_dpm_table dclk_table; 99 struct smu_13_0_dpm_table dcef_table; 100 struct smu_13_0_dpm_table pixel_table; 101 struct smu_13_0_dpm_table display_table; 102 struct smu_13_0_dpm_table phy_table; 103 struct smu_13_0_dpm_table fclk_table; 104 struct smu_13_0_pcie_table pcie_table; 105 }; 106 107 struct smu_13_0_dpm_context { 108 struct smu_13_0_dpm_tables dpm_tables; 109 uint32_t workload_policy_mask; 110 uint32_t dcef_min_ds_clk; 111 }; 112 113 enum smu_13_0_power_state { 114 SMU_13_0_POWER_STATE__D0 = 0, 115 SMU_13_0_POWER_STATE__D1, 116 SMU_13_0_POWER_STATE__D3, /* Sleep*/ 117 SMU_13_0_POWER_STATE__D4, /* Hibernate*/ 118 SMU_13_0_POWER_STATE__D5, /* Power off*/ 119 }; 120 121 struct smu_13_0_power_context { 122 uint32_t power_source; 123 uint8_t in_power_limit_boost_mode; 124 enum smu_13_0_power_state power_state; 125 }; 126 127 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 128 129 int smu_v13_0_init_microcode(struct smu_context *smu); 130 131 void smu_v13_0_fini_microcode(struct smu_context *smu); 132 133 int smu_v13_0_load_microcode(struct smu_context *smu); 134 135 int smu_v13_0_init_smc_tables(struct smu_context *smu); 136 137 int smu_v13_0_fini_smc_tables(struct smu_context *smu); 138 139 int smu_v13_0_init_power(struct smu_context *smu); 140 141 int smu_v13_0_fini_power(struct smu_context *smu); 142 143 int smu_v13_0_check_fw_status(struct smu_context *smu); 144 145 int smu_v13_0_setup_pptable(struct smu_context *smu); 146 147 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu); 148 149 int smu_v13_0_check_fw_version(struct smu_context *smu); 150 151 int smu_v13_0_set_driver_table_location(struct smu_context *smu); 152 153 int smu_v13_0_set_tool_table_location(struct smu_context *smu); 154 155 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu); 156 157 int smu_v13_0_system_features_control(struct smu_context *smu, 158 bool en); 159 160 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count); 161 162 int smu_v13_0_set_allowed_mask(struct smu_context *smu); 163 164 int smu_v13_0_notify_display_change(struct smu_context *smu); 165 166 int smu_v13_0_get_current_power_limit(struct smu_context *smu, 167 uint32_t *power_limit); 168 169 int smu_v13_0_set_power_limit(struct smu_context *smu, 170 enum smu_ppt_limit_type limit_type, 171 uint32_t limit); 172 173 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu); 174 175 int smu_v13_0_enable_thermal_alert(struct smu_context *smu); 176 177 int smu_v13_0_disable_thermal_alert(struct smu_context *smu); 178 179 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value); 180 181 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk); 182 183 int 184 smu_v13_0_display_clock_voltage_request(struct smu_context *smu, 185 struct pp_display_clock_request 186 *clock_req); 187 188 uint32_t 189 smu_v13_0_get_fan_control_mode(struct smu_context *smu); 190 191 int 192 smu_v13_0_set_fan_control_mode(struct smu_context *smu, 193 uint32_t mode); 194 195 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu, 196 uint32_t speed); 197 198 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu, 199 uint32_t speed); 200 201 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu, 202 uint32_t pstate); 203 204 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable); 205 206 int smu_v13_0_register_irq_handler(struct smu_context *smu); 207 208 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu); 209 210 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 211 struct pp_smu_nv_clock_table *max_clocks); 212 213 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu, 214 enum smu_baco_seq baco_seq); 215 216 bool smu_v13_0_baco_is_support(struct smu_context *smu); 217 218 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu); 219 220 int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 221 222 int smu_v13_0_baco_enter(struct smu_context *smu); 223 int smu_v13_0_baco_exit(struct smu_context *smu); 224 225 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 226 uint32_t *min, uint32_t *max); 227 228 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 229 uint32_t min, uint32_t max); 230 231 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu, 232 enum smu_clk_type clk_type, 233 uint32_t min, 234 uint32_t max); 235 236 int smu_v13_0_set_performance_level(struct smu_context *smu, 237 enum amd_dpm_forced_level level); 238 239 int smu_v13_0_set_power_source(struct smu_context *smu, 240 enum smu_power_src_type power_src); 241 242 int smu_v13_0_set_single_dpm_table(struct smu_context *smu, 243 enum smu_clk_type clk_type, 244 struct smu_13_0_dpm_table *single_dpm_table); 245 246 int smu_v13_0_get_dpm_level_range(struct smu_context *smu, 247 enum smu_clk_type clk_type, 248 uint32_t *min_value, 249 uint32_t *max_value); 250 251 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu); 252 253 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu); 254 255 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu); 256 257 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu); 258 259 int smu_v13_0_gfx_ulv_control(struct smu_context *smu, 260 bool enablement); 261 262 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 263 uint64_t event_arg); 264 265 int smu_v13_0_set_vcn_enable(struct smu_context *smu, 266 bool enable); 267 268 int smu_v13_0_set_jpeg_enable(struct smu_context *smu, 269 bool enable); 270 271 int smu_v13_0_init_pptable_microcode(struct smu_context *smu); 272 273 int smu_v13_0_run_btc(struct smu_context *smu); 274 275 int smu_v13_0_deep_sleep_control(struct smu_context *smu, 276 bool enablement); 277 278 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu); 279 280 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, 281 enum PP_OD_DPM_TABLE_COMMAND type, 282 long input[], 283 uint32_t size); 284 285 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu); 286 287 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu); 288 289 int smu_v13_0_mode1_reset(struct smu_context *smu); 290 291 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu, 292 void **table, 293 uint32_t *size, 294 uint32_t pptable_id); 295 296 #endif 297 #endif 298
