Searched refs:SKL_DPLL0 (Results 1 – 2 of 2) sorted by relevance
893 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_update()894 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_update()895 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != in skl_dpll0_update()896 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) in skl_dpll0_update()899 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { in skl_dpll0_update()900 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): in skl_dpll0_update()901 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): in skl_dpll0_update()902 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): in skl_dpll0_update()903 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): in skl_dpll0_update()906 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): in skl_dpll0_update()[all …]
322 #define SKL_DPLL0 0 macro
