1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 MaxLinear, Inc.
4 *
5 * This driver is a hardware monitoring driver for PVT controller
6 * (MR75203) which is used to configure & control Moortec embedded
7 * analog IP to enable multiple embedded temperature sensor(TS),
8 * voltage monitor(VM) & process detector(PD) modules.
9 */
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/hwmon.h>
14 #include <linux/module.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/mutex.h>
17 #include <linux/platform_device.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/units.h>
23
24 /* PVT Common register */
25 #define PVT_IP_CONFIG 0x04
26 #define TS_NUM_MSK GENMASK(4, 0)
27 #define TS_NUM_SFT 0
28 #define PD_NUM_MSK GENMASK(12, 8)
29 #define PD_NUM_SFT 8
30 #define VM_NUM_MSK GENMASK(20, 16)
31 #define VM_NUM_SFT 16
32 #define CH_NUM_MSK GENMASK(31, 24)
33 #define CH_NUM_SFT 24
34
35 #define VM_NUM_MAX (VM_NUM_MSK >> VM_NUM_SFT)
36
37 /* Macro Common Register */
38 #define CLK_SYNTH 0x00
39 #define CLK_SYNTH_LO_SFT 0
40 #define CLK_SYNTH_HI_SFT 8
41 #define CLK_SYNTH_HOLD_SFT 16
42 #define CLK_SYNTH_EN BIT(24)
43 #define CLK_SYS_CYCLES_MAX 514
44 #define CLK_SYS_CYCLES_MIN 2
45
46 #define SDIF_DISABLE 0x04
47
48 #define SDIF_STAT 0x08
49 #define SDIF_BUSY BIT(0)
50 #define SDIF_LOCK BIT(1)
51
52 #define SDIF_W 0x0c
53 #define SDIF_PROG BIT(31)
54 #define SDIF_WRN_W BIT(27)
55 #define SDIF_WRN_R 0x00
56 #define SDIF_ADDR_SFT 24
57
58 #define SDIF_HALT 0x10
59 #define SDIF_CTRL 0x14
60 #define SDIF_SMPL_CTRL 0x20
61
62 /* TS & PD Individual Macro Register */
63 #define COM_REG_SIZE 0x40
64
65 #define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n))
66 #define SDIF_SMPL_DONE BIT(0)
67
68 #define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n))
69 #define SAMPLE_DATA_MSK GENMASK(15, 0)
70
71 #define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n))
72
73 /* VM Individual Macro Register */
74 #define VM_COM_REG_SIZE 0x200
75 #define VM_SDIF_DONE(vm) (VM_COM_REG_SIZE + 0x34 + 0x200 * (vm))
76 #define VM_SDIF_DATA(vm, ch) \
77 (VM_COM_REG_SIZE + 0x40 + 0x200 * (vm) + 0x4 * (ch))
78
79 /* SDA Slave Register */
80 #define IP_CTRL 0x00
81 #define IP_RST_REL BIT(1)
82 #define IP_RUN_CONT BIT(3)
83 #define IP_AUTO BIT(8)
84 #define IP_VM_MODE BIT(10)
85
86 #define IP_CFG 0x01
87 #define CFG0_MODE_2 BIT(0)
88 #define CFG0_PARALLEL_OUT 0
89 #define CFG0_12_BIT 0
90 #define CFG1_VOL_MEAS_MODE 0
91 #define CFG1_PARALLEL_OUT 0
92 #define CFG1_14_BIT 0
93
94 #define IP_DATA 0x03
95
96 #define IP_POLL 0x04
97 #define VM_CH_INIT BIT(20)
98 #define VM_CH_REQ BIT(21)
99
100 #define IP_TMR 0x05
101 #define POWER_DELAY_CYCLE_256 0x100
102 #define POWER_DELAY_CYCLE_64 0x40
103
104 #define PVT_POLL_DELAY_US 20
105 #define PVT_POLL_TIMEOUT_US 20000
106 #define PVT_CONV_BITS 10
107 #define PVT_N_CONST 90
108 #define PVT_R_CONST 245805
109
110 #define PVT_TEMP_MIN_mC -40000
111 #define PVT_TEMP_MAX_mC 125000
112
113 /* Temperature coefficients for series 5 */
114 #define PVT_SERIES5_H_CONST 200000
115 #define PVT_SERIES5_G_CONST 60000
116 #define PVT_SERIES5_J_CONST -100
117 #define PVT_SERIES5_CAL5_CONST 4094
118
119 /* Temperature coefficients for series 6 */
120 #define PVT_SERIES6_H_CONST 249400
121 #define PVT_SERIES6_G_CONST 57400
122 #define PVT_SERIES6_J_CONST 0
123 #define PVT_SERIES6_CAL5_CONST 4096
124
125 #define TEMPERATURE_SENSOR_SERIES_5 5
126 #define TEMPERATURE_SENSOR_SERIES_6 6
127
128 #define PRE_SCALER_X1 1
129 #define PRE_SCALER_X2 2
130
131 /**
132 * struct voltage_device - VM single input parameters.
133 * @vm_map: Map channel number to VM index.
134 * @ch_map: Map channel number to channel index.
135 * @pre_scaler: Pre scaler value (1 or 2) used to normalize the voltage output
136 * result.
137 *
138 * The structure provides mapping between channel-number (0..N-1) to VM-index
139 * (0..num_vm-1) and channel-index (0..ch_num-1) where N = num_vm * ch_num.
140 * It also provides normalization factor for the VM equation.
141 */
142 struct voltage_device {
143 u32 vm_map;
144 u32 ch_map;
145 u32 pre_scaler;
146 };
147
148 /**
149 * struct voltage_channels - VM channel count.
150 * @total: Total number of channels in all VMs.
151 * @max: Maximum number of channels among all VMs.
152 *
153 * The structure provides channel count information across all VMs.
154 */
155 struct voltage_channels {
156 u32 total;
157 u8 max;
158 };
159
160 struct temp_coeff {
161 u32 h;
162 u32 g;
163 u32 cal5;
164 s32 j;
165 };
166
167 struct pvt_device {
168 struct regmap *c_map;
169 struct regmap *t_map;
170 struct regmap *p_map;
171 struct regmap *v_map;
172 struct clk *clk;
173 struct reset_control *rst;
174 struct dentry *dbgfs_dir;
175 struct voltage_device *vd;
176 struct voltage_channels vm_channels;
177 struct temp_coeff ts_coeff;
178 u32 t_num;
179 u32 p_num;
180 u32 v_num;
181 u32 ip_freq;
182 };
183
pvt_ts_coeff_j_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)184 static ssize_t pvt_ts_coeff_j_read(struct file *file, char __user *user_buf,
185 size_t count, loff_t *ppos)
186 {
187 struct pvt_device *pvt = file->private_data;
188 unsigned int len;
189 char buf[13];
190
191 len = scnprintf(buf, sizeof(buf), "%d\n", pvt->ts_coeff.j);
192
193 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
194 }
195
pvt_ts_coeff_j_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)196 static ssize_t pvt_ts_coeff_j_write(struct file *file,
197 const char __user *user_buf,
198 size_t count, loff_t *ppos)
199 {
200 struct pvt_device *pvt = file->private_data;
201 int ret;
202
203 ret = kstrtos32_from_user(user_buf, count, 0, &pvt->ts_coeff.j);
204 if (ret)
205 return ret;
206
207 return count;
208 }
209
210 static const struct file_operations pvt_ts_coeff_j_fops = {
211 .read = pvt_ts_coeff_j_read,
212 .write = pvt_ts_coeff_j_write,
213 .open = simple_open,
214 .owner = THIS_MODULE,
215 .llseek = default_llseek,
216 };
217
devm_pvt_ts_dbgfs_remove(void * data)218 static void devm_pvt_ts_dbgfs_remove(void *data)
219 {
220 struct pvt_device *pvt = (struct pvt_device *)data;
221
222 debugfs_remove_recursive(pvt->dbgfs_dir);
223 pvt->dbgfs_dir = NULL;
224 }
225
pvt_ts_dbgfs_create(struct pvt_device * pvt,struct device * dev)226 static int pvt_ts_dbgfs_create(struct pvt_device *pvt, struct device *dev)
227 {
228 pvt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
229
230 debugfs_create_u32("ts_coeff_h", 0644, pvt->dbgfs_dir,
231 &pvt->ts_coeff.h);
232 debugfs_create_u32("ts_coeff_g", 0644, pvt->dbgfs_dir,
233 &pvt->ts_coeff.g);
234 debugfs_create_u32("ts_coeff_cal5", 0644, pvt->dbgfs_dir,
235 &pvt->ts_coeff.cal5);
236 debugfs_create_file("ts_coeff_j", 0644, pvt->dbgfs_dir, pvt,
237 &pvt_ts_coeff_j_fops);
238
239 return devm_add_action_or_reset(dev, devm_pvt_ts_dbgfs_remove, pvt);
240 }
241
pvt_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)242 static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type,
243 u32 attr, int channel)
244 {
245 switch (type) {
246 case hwmon_temp:
247 if (attr == hwmon_temp_input)
248 return 0444;
249 break;
250 case hwmon_in:
251 if (attr == hwmon_in_input)
252 return 0444;
253 break;
254 default:
255 break;
256 }
257 return 0;
258 }
259
pvt_calc_temp(struct pvt_device * pvt,u32 nbs)260 static long pvt_calc_temp(struct pvt_device *pvt, u32 nbs)
261 {
262 /*
263 * Convert the register value to degrees centigrade temperature:
264 * T = G + H * (n / cal5 - 0.5) + J * F
265 */
266 struct temp_coeff *ts_coeff = &pvt->ts_coeff;
267
268 s64 tmp = ts_coeff->g +
269 div_s64(ts_coeff->h * (s64)nbs, ts_coeff->cal5) -
270 ts_coeff->h / 2 +
271 div_s64(ts_coeff->j * (s64)pvt->ip_freq, HZ_PER_MHZ);
272
273 return clamp_val(tmp, PVT_TEMP_MIN_mC, PVT_TEMP_MAX_mC);
274 }
275
pvt_read_temp(struct device * dev,u32 attr,int channel,long * val)276 static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val)
277 {
278 struct pvt_device *pvt = dev_get_drvdata(dev);
279 struct regmap *t_map = pvt->t_map;
280 u32 stat, nbs;
281 int ret;
282
283 switch (attr) {
284 case hwmon_temp_input:
285 ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel),
286 stat, stat & SDIF_SMPL_DONE,
287 PVT_POLL_DELAY_US,
288 PVT_POLL_TIMEOUT_US);
289 if (ret)
290 return ret;
291
292 ret = regmap_read(t_map, SDIF_DATA(channel), &nbs);
293 if (ret < 0)
294 return ret;
295
296 nbs &= SAMPLE_DATA_MSK;
297
298 /*
299 * Convert the register value to
300 * degrees centigrade temperature
301 */
302 *val = pvt_calc_temp(pvt, nbs);
303
304 return 0;
305 default:
306 return -EOPNOTSUPP;
307 }
308 }
309
pvt_read_in(struct device * dev,u32 attr,int channel,long * val)310 static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val)
311 {
312 struct pvt_device *pvt = dev_get_drvdata(dev);
313 struct regmap *v_map = pvt->v_map;
314 u32 n, stat, pre_scaler;
315 u8 vm_idx, ch_idx;
316 int ret;
317
318 if (channel >= pvt->vm_channels.total)
319 return -EINVAL;
320
321 vm_idx = pvt->vd[channel].vm_map;
322 ch_idx = pvt->vd[channel].ch_map;
323
324 switch (attr) {
325 case hwmon_in_input:
326 ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx),
327 stat, stat & SDIF_SMPL_DONE,
328 PVT_POLL_DELAY_US,
329 PVT_POLL_TIMEOUT_US);
330 if (ret)
331 return ret;
332
333 ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx, ch_idx), &n);
334 if (ret < 0)
335 return ret;
336
337 n &= SAMPLE_DATA_MSK;
338 pre_scaler = pvt->vd[channel].pre_scaler;
339 /*
340 * Convert the N bitstream count into voltage.
341 * To support negative voltage calculation for 64bit machines
342 * n must be cast to long, since n and *val differ both in
343 * signedness and in size.
344 * Division is used instead of right shift, because for signed
345 * numbers, the sign bit is used to fill the vacated bit
346 * positions, and if the number is negative, 1 is used.
347 * BIT(x) may not be used instead of (1 << x) because it's
348 * unsigned.
349 */
350 *val = pre_scaler * (PVT_N_CONST * (long)n - PVT_R_CONST) /
351 (1 << PVT_CONV_BITS);
352
353 return 0;
354 default:
355 return -EOPNOTSUPP;
356 }
357 }
358
pvt_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)359 static int pvt_read(struct device *dev, enum hwmon_sensor_types type,
360 u32 attr, int channel, long *val)
361 {
362 switch (type) {
363 case hwmon_temp:
364 return pvt_read_temp(dev, attr, channel, val);
365 case hwmon_in:
366 return pvt_read_in(dev, attr, channel, val);
367 default:
368 return -EOPNOTSUPP;
369 }
370 }
371
372 static struct hwmon_channel_info pvt_temp = {
373 .type = hwmon_temp,
374 };
375
376 static struct hwmon_channel_info pvt_in = {
377 .type = hwmon_in,
378 };
379
380 static const struct hwmon_ops pvt_hwmon_ops = {
381 .is_visible = pvt_is_visible,
382 .read = pvt_read,
383 };
384
385 static struct hwmon_chip_info pvt_chip_info = {
386 .ops = &pvt_hwmon_ops,
387 };
388
pvt_init(struct pvt_device * pvt)389 static int pvt_init(struct pvt_device *pvt)
390 {
391 u16 sys_freq, key, middle, low = 4, high = 8;
392 struct regmap *t_map = pvt->t_map;
393 struct regmap *p_map = pvt->p_map;
394 struct regmap *v_map = pvt->v_map;
395 u32 t_num = pvt->t_num;
396 u32 p_num = pvt->p_num;
397 u32 v_num = pvt->v_num;
398 u32 clk_synth, val;
399 int ret;
400
401 sys_freq = clk_get_rate(pvt->clk) / HZ_PER_MHZ;
402 while (high >= low) {
403 middle = (low + high + 1) / 2;
404 key = DIV_ROUND_CLOSEST(sys_freq, middle);
405 if (key > CLK_SYS_CYCLES_MAX) {
406 low = middle + 1;
407 continue;
408 } else if (key < CLK_SYS_CYCLES_MIN) {
409 high = middle - 1;
410 continue;
411 } else {
412 break;
413 }
414 }
415
416 /*
417 * The system supports 'clk_sys' to 'clk_ip' frequency ratios
418 * from 2:1 to 512:1
419 */
420 key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2;
421
422 clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT |
423 (key >> 1) << CLK_SYNTH_HI_SFT |
424 (key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN;
425
426 pvt->ip_freq = clk_get_rate(pvt->clk) / (key + 2);
427
428 if (t_num) {
429 ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0);
430 if (ret < 0)
431 return ret;
432
433 ret = regmap_write(t_map, SDIF_HALT, 0x0);
434 if (ret < 0)
435 return ret;
436
437 ret = regmap_write(t_map, CLK_SYNTH, clk_synth);
438 if (ret < 0)
439 return ret;
440
441 ret = regmap_write(t_map, SDIF_DISABLE, 0x0);
442 if (ret < 0)
443 return ret;
444
445 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
446 val, !(val & SDIF_BUSY),
447 PVT_POLL_DELAY_US,
448 PVT_POLL_TIMEOUT_US);
449 if (ret)
450 return ret;
451
452 val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT |
453 IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
454 ret = regmap_write(t_map, SDIF_W, val);
455 if (ret < 0)
456 return ret;
457
458 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
459 val, !(val & SDIF_BUSY),
460 PVT_POLL_DELAY_US,
461 PVT_POLL_TIMEOUT_US);
462 if (ret)
463 return ret;
464
465 val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT |
466 SDIF_WRN_W | SDIF_PROG;
467 ret = regmap_write(t_map, SDIF_W, val);
468 if (ret < 0)
469 return ret;
470
471 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
472 val, !(val & SDIF_BUSY),
473 PVT_POLL_DELAY_US,
474 PVT_POLL_TIMEOUT_US);
475 if (ret)
476 return ret;
477
478 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO |
479 IP_CTRL << SDIF_ADDR_SFT |
480 SDIF_WRN_W | SDIF_PROG;
481 ret = regmap_write(t_map, SDIF_W, val);
482 if (ret < 0)
483 return ret;
484 }
485
486 if (p_num) {
487 ret = regmap_write(p_map, SDIF_HALT, 0x0);
488 if (ret < 0)
489 return ret;
490
491 ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1);
492 if (ret < 0)
493 return ret;
494
495 ret = regmap_write(p_map, CLK_SYNTH, clk_synth);
496 if (ret < 0)
497 return ret;
498 }
499
500 if (v_num) {
501 ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0);
502 if (ret < 0)
503 return ret;
504
505 ret = regmap_write(v_map, SDIF_HALT, 0x0);
506 if (ret < 0)
507 return ret;
508
509 ret = regmap_write(v_map, CLK_SYNTH, clk_synth);
510 if (ret < 0)
511 return ret;
512
513 ret = regmap_write(v_map, SDIF_DISABLE, 0x0);
514 if (ret < 0)
515 return ret;
516
517 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
518 val, !(val & SDIF_BUSY),
519 PVT_POLL_DELAY_US,
520 PVT_POLL_TIMEOUT_US);
521 if (ret)
522 return ret;
523
524 val = (BIT(pvt->vm_channels.max) - 1) | VM_CH_INIT |
525 IP_POLL << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
526 ret = regmap_write(v_map, SDIF_W, val);
527 if (ret < 0)
528 return ret;
529
530 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
531 val, !(val & SDIF_BUSY),
532 PVT_POLL_DELAY_US,
533 PVT_POLL_TIMEOUT_US);
534 if (ret)
535 return ret;
536
537 val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT |
538 CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT |
539 SDIF_WRN_W | SDIF_PROG;
540 ret = regmap_write(v_map, SDIF_W, val);
541 if (ret < 0)
542 return ret;
543
544 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
545 val, !(val & SDIF_BUSY),
546 PVT_POLL_DELAY_US,
547 PVT_POLL_TIMEOUT_US);
548 if (ret)
549 return ret;
550
551 val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT |
552 SDIF_WRN_W | SDIF_PROG;
553 ret = regmap_write(v_map, SDIF_W, val);
554 if (ret < 0)
555 return ret;
556
557 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
558 val, !(val & SDIF_BUSY),
559 PVT_POLL_DELAY_US,
560 PVT_POLL_TIMEOUT_US);
561 if (ret)
562 return ret;
563
564 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE |
565 IP_CTRL << SDIF_ADDR_SFT |
566 SDIF_WRN_W | SDIF_PROG;
567 ret = regmap_write(v_map, SDIF_W, val);
568 if (ret < 0)
569 return ret;
570 }
571
572 return 0;
573 }
574
575 static struct regmap_config pvt_regmap_config = {
576 .reg_bits = 32,
577 .reg_stride = 4,
578 .val_bits = 32,
579 };
580
pvt_get_regmap(struct platform_device * pdev,char * reg_name,struct pvt_device * pvt)581 static int pvt_get_regmap(struct platform_device *pdev, char *reg_name,
582 struct pvt_device *pvt)
583 {
584 struct device *dev = &pdev->dev;
585 struct regmap **reg_map;
586 void __iomem *io_base;
587
588 if (!strcmp(reg_name, "common"))
589 reg_map = &pvt->c_map;
590 else if (!strcmp(reg_name, "ts"))
591 reg_map = &pvt->t_map;
592 else if (!strcmp(reg_name, "pd"))
593 reg_map = &pvt->p_map;
594 else if (!strcmp(reg_name, "vm"))
595 reg_map = &pvt->v_map;
596 else
597 return -EINVAL;
598
599 io_base = devm_platform_ioremap_resource_byname(pdev, reg_name);
600 if (IS_ERR(io_base))
601 return PTR_ERR(io_base);
602
603 pvt_regmap_config.name = reg_name;
604 *reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config);
605 if (IS_ERR(*reg_map)) {
606 dev_err(dev, "failed to init register map\n");
607 return PTR_ERR(*reg_map);
608 }
609
610 return 0;
611 }
612
pvt_reset_control_assert(void * data)613 static void pvt_reset_control_assert(void *data)
614 {
615 struct pvt_device *pvt = data;
616
617 reset_control_assert(pvt->rst);
618 }
619
pvt_reset_control_deassert(struct device * dev,struct pvt_device * pvt)620 static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt)
621 {
622 int ret;
623
624 ret = reset_control_deassert(pvt->rst);
625 if (ret)
626 return ret;
627
628 return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt);
629 }
630
pvt_get_active_channel(struct device * dev,struct pvt_device * pvt,u32 vm_num,u32 ch_num,u8 * vm_idx)631 static int pvt_get_active_channel(struct device *dev, struct pvt_device *pvt,
632 u32 vm_num, u32 ch_num, u8 *vm_idx)
633 {
634 u8 vm_active_ch[VM_NUM_MAX];
635 int ret, i, j, k;
636
637 ret = device_property_read_u8_array(dev, "moortec,vm-active-channels",
638 vm_active_ch, vm_num);
639 if (ret) {
640 /*
641 * Incase "moortec,vm-active-channels" property is not defined,
642 * we assume each VM sensor has all of its channels active.
643 */
644 memset(vm_active_ch, ch_num, vm_num);
645 pvt->vm_channels.max = ch_num;
646 pvt->vm_channels.total = ch_num * vm_num;
647 } else {
648 for (i = 0; i < vm_num; i++) {
649 if (vm_active_ch[i] > ch_num) {
650 dev_err(dev, "invalid active channels: %u\n",
651 vm_active_ch[i]);
652 return -EINVAL;
653 }
654
655 pvt->vm_channels.total += vm_active_ch[i];
656
657 if (vm_active_ch[i] > pvt->vm_channels.max)
658 pvt->vm_channels.max = vm_active_ch[i];
659 }
660 }
661
662 /*
663 * Map between the channel-number to VM-index and channel-index.
664 * Example - 3 VMs, "moortec,vm_active_ch" = <5 2 4>:
665 * vm_map = [0 0 0 0 0 1 1 2 2 2 2]
666 * ch_map = [0 1 2 3 4 0 1 0 1 2 3]
667 */
668 pvt->vd = devm_kcalloc(dev, pvt->vm_channels.total, sizeof(*pvt->vd),
669 GFP_KERNEL);
670 if (!pvt->vd)
671 return -ENOMEM;
672
673 k = 0;
674 for (i = 0; i < vm_num; i++) {
675 for (j = 0; j < vm_active_ch[i]; j++) {
676 pvt->vd[k].vm_map = vm_idx[i];
677 pvt->vd[k].ch_map = j;
678 k++;
679 }
680 }
681
682 return 0;
683 }
684
pvt_get_pre_scaler(struct device * dev,struct pvt_device * pvt)685 static int pvt_get_pre_scaler(struct device *dev, struct pvt_device *pvt)
686 {
687 u8 *pre_scaler_ch_list;
688 int i, ret, num_ch;
689 u32 channel;
690
691 /* Set default pre-scaler value to be 1. */
692 for (i = 0; i < pvt->vm_channels.total; i++)
693 pvt->vd[i].pre_scaler = PRE_SCALER_X1;
694
695 /* Get number of channels configured in "moortec,vm-pre-scaler-x2". */
696 num_ch = device_property_count_u8(dev, "moortec,vm-pre-scaler-x2");
697 if (num_ch <= 0)
698 return 0;
699
700 pre_scaler_ch_list = kcalloc(num_ch, sizeof(*pre_scaler_ch_list),
701 GFP_KERNEL);
702 if (!pre_scaler_ch_list)
703 return -ENOMEM;
704
705 /* Get list of all channels that have pre-scaler of 2. */
706 ret = device_property_read_u8_array(dev, "moortec,vm-pre-scaler-x2",
707 pre_scaler_ch_list, num_ch);
708 if (ret)
709 goto out;
710
711 for (i = 0; i < num_ch; i++) {
712 channel = pre_scaler_ch_list[i];
713 pvt->vd[channel].pre_scaler = PRE_SCALER_X2;
714 }
715
716 out:
717 kfree(pre_scaler_ch_list);
718
719 return ret;
720 }
721
pvt_set_temp_coeff(struct device * dev,struct pvt_device * pvt)722 static int pvt_set_temp_coeff(struct device *dev, struct pvt_device *pvt)
723 {
724 struct temp_coeff *ts_coeff = &pvt->ts_coeff;
725 u32 series;
726 int ret;
727
728 /* Incase ts-series property is not defined, use default 5. */
729 ret = device_property_read_u32(dev, "moortec,ts-series", &series);
730 if (ret)
731 series = TEMPERATURE_SENSOR_SERIES_5;
732
733 switch (series) {
734 case TEMPERATURE_SENSOR_SERIES_5:
735 ts_coeff->h = PVT_SERIES5_H_CONST;
736 ts_coeff->g = PVT_SERIES5_G_CONST;
737 ts_coeff->j = PVT_SERIES5_J_CONST;
738 ts_coeff->cal5 = PVT_SERIES5_CAL5_CONST;
739 break;
740 case TEMPERATURE_SENSOR_SERIES_6:
741 ts_coeff->h = PVT_SERIES6_H_CONST;
742 ts_coeff->g = PVT_SERIES6_G_CONST;
743 ts_coeff->j = PVT_SERIES6_J_CONST;
744 ts_coeff->cal5 = PVT_SERIES6_CAL5_CONST;
745 break;
746 default:
747 dev_err(dev, "invalid temperature sensor series (%u)\n",
748 series);
749 return -EINVAL;
750 }
751
752 dev_dbg(dev, "temperature sensor series = %u\n", series);
753
754 /* Override ts-coeff-h/g/j/cal5 if they are defined. */
755 device_property_read_u32(dev, "moortec,ts-coeff-h", &ts_coeff->h);
756 device_property_read_u32(dev, "moortec,ts-coeff-g", &ts_coeff->g);
757 device_property_read_u32(dev, "moortec,ts-coeff-j", &ts_coeff->j);
758 device_property_read_u32(dev, "moortec,ts-coeff-cal5", &ts_coeff->cal5);
759
760 dev_dbg(dev, "ts-coeff: h = %u, g = %u, j = %d, cal5 = %u\n",
761 ts_coeff->h, ts_coeff->g, ts_coeff->j, ts_coeff->cal5);
762
763 return 0;
764 }
765
mr75203_probe(struct platform_device * pdev)766 static int mr75203_probe(struct platform_device *pdev)
767 {
768 u32 ts_num, vm_num, pd_num, ch_num, val, index, i;
769 const struct hwmon_channel_info **pvt_info;
770 struct device *dev = &pdev->dev;
771 u32 *temp_config, *in_config;
772 struct device *hwmon_dev;
773 struct pvt_device *pvt;
774 int ret;
775
776 pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL);
777 if (!pvt)
778 return -ENOMEM;
779
780 ret = pvt_get_regmap(pdev, "common", pvt);
781 if (ret)
782 return ret;
783
784 pvt->clk = devm_clk_get_enabled(dev, NULL);
785 if (IS_ERR(pvt->clk))
786 return dev_err_probe(dev, PTR_ERR(pvt->clk), "failed to get clock\n");
787
788 pvt->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
789 if (IS_ERR(pvt->rst))
790 return dev_err_probe(dev, PTR_ERR(pvt->rst),
791 "failed to get reset control\n");
792
793 if (pvt->rst) {
794 ret = pvt_reset_control_deassert(dev, pvt);
795 if (ret)
796 return dev_err_probe(dev, ret,
797 "cannot deassert reset control\n");
798 }
799
800 ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val);
801 if (ret < 0)
802 return ret;
803
804 ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT;
805 pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT;
806 vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT;
807 ch_num = (val & CH_NUM_MSK) >> CH_NUM_SFT;
808 pvt->t_num = ts_num;
809 pvt->p_num = pd_num;
810 pvt->v_num = vm_num;
811 val = 0;
812 if (ts_num)
813 val++;
814 if (vm_num)
815 val++;
816 if (!val)
817 return -ENODEV;
818
819 pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL);
820 if (!pvt_info)
821 return -ENOMEM;
822 pvt_info[0] = HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ);
823 index = 1;
824
825 if (ts_num) {
826 ret = pvt_get_regmap(pdev, "ts", pvt);
827 if (ret)
828 return ret;
829
830 ret = pvt_set_temp_coeff(dev, pvt);
831 if (ret)
832 return ret;
833
834 temp_config = devm_kcalloc(dev, ts_num + 1,
835 sizeof(*temp_config), GFP_KERNEL);
836 if (!temp_config)
837 return -ENOMEM;
838
839 memset32(temp_config, HWMON_T_INPUT, ts_num);
840 pvt_temp.config = temp_config;
841 pvt_info[index++] = &pvt_temp;
842
843 pvt_ts_dbgfs_create(pvt, dev);
844 }
845
846 if (pd_num) {
847 ret = pvt_get_regmap(pdev, "pd", pvt);
848 if (ret)
849 return ret;
850 }
851
852 if (vm_num) {
853 u8 vm_idx[VM_NUM_MAX];
854
855 ret = pvt_get_regmap(pdev, "vm", pvt);
856 if (ret)
857 return ret;
858
859 ret = device_property_read_u8_array(dev, "intel,vm-map", vm_idx,
860 vm_num);
861 if (ret) {
862 /*
863 * Incase intel,vm-map property is not defined, we
864 * assume incremental channel numbers.
865 */
866 for (i = 0; i < vm_num; i++)
867 vm_idx[i] = i;
868 } else {
869 for (i = 0; i < vm_num; i++)
870 if (vm_idx[i] >= vm_num || vm_idx[i] == 0xff) {
871 pvt->v_num = i;
872 vm_num = i;
873 break;
874 }
875 }
876
877 ret = pvt_get_active_channel(dev, pvt, vm_num, ch_num, vm_idx);
878 if (ret)
879 return ret;
880
881 ret = pvt_get_pre_scaler(dev, pvt);
882 if (ret)
883 return ret;
884
885 in_config = devm_kcalloc(dev, pvt->vm_channels.total + 1,
886 sizeof(*in_config), GFP_KERNEL);
887 if (!in_config)
888 return -ENOMEM;
889
890 memset32(in_config, HWMON_I_INPUT, pvt->vm_channels.total);
891 in_config[pvt->vm_channels.total] = 0;
892 pvt_in.config = in_config;
893
894 pvt_info[index++] = &pvt_in;
895 }
896
897 ret = pvt_init(pvt);
898 if (ret) {
899 dev_err(dev, "failed to init pvt: %d\n", ret);
900 return ret;
901 }
902
903 pvt_chip_info.info = pvt_info;
904 hwmon_dev = devm_hwmon_device_register_with_info(dev, "pvt",
905 pvt,
906 &pvt_chip_info,
907 NULL);
908
909 return PTR_ERR_OR_ZERO(hwmon_dev);
910 }
911
912 static const struct of_device_id moortec_pvt_of_match[] = {
913 { .compatible = "moortec,mr75203" },
914 { }
915 };
916 MODULE_DEVICE_TABLE(of, moortec_pvt_of_match);
917
918 static struct platform_driver moortec_pvt_driver = {
919 .driver = {
920 .name = "moortec-pvt",
921 .of_match_table = moortec_pvt_of_match,
922 },
923 .probe = mr75203_probe,
924 };
925 module_platform_driver(moortec_pvt_driver);
926
927 MODULE_LICENSE("GPL v2");
928
