Home
last modified time | relevance | path

Searched refs:REG_SIZE (Results 1 – 21 of 21) sorted by relevance

/Linux-v6.1/drivers/irqchip/
Dqcom-irq-combiner.c24 #define REG_SIZE 32 macro
41 return reg * REG_SIZE + bit; in irq_nr()
82 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_mask_irq()
84 clear_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_mask_irq()
90 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_unmask_irq()
92 set_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_unmask_irq()
186 (reg->bit_width > REG_SIZE)) { in get_registers_cb()
192 vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE); in get_registers_cb()
/Linux-v6.1/sound/soc/tegra/
Dtegra210_mvc.h92 #define REG_SIZE 4 macro
94 #define TEGRA210_MVC_REG_OFFSET(reg, i) (reg + (REG_SIZE * i))
96 #define TEGRA210_MVC_GET_CHAN(reg, base) (((reg) - (base)) / REG_SIZE)
/Linux-v6.1/drivers/hwmon/
Dultra45_env.c37 #define REG_SIZE 0x42UL macro
264 p->regs = of_ioremap(&op->resource[0], 0, REG_SIZE, "pic16f747"); in env_probe()
288 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_probe()
300 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_remove()
/Linux-v6.1/drivers/pinctrl/qcom/
Dpinctrl-ipq8074.c20 #define REG_SIZE 0x1000 macro
39 .ctl_reg = REG_SIZE * id, \
40 .io_reg = 0x4 + REG_SIZE * id, \
41 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
42 .intr_status_reg = 0xc + REG_SIZE * id, \
43 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-ipq6018.c20 #define REG_SIZE 0x1000 macro
39 .ctl_reg = REG_SIZE * id, \
40 .io_reg = 0x4 + REG_SIZE * id, \
41 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
42 .intr_status_reg = 0xc + REG_SIZE * id, \
43 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-sdx55.c20 #define REG_SIZE 0x1000 macro
40 .ctl_reg = REG_SIZE * id, \
41 .io_reg = 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
43 .intr_status_reg = 0xc + REG_SIZE * id, \
44 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-sdx65.c21 #define REG_SIZE 0x1000 macro
40 .ctl_reg = REG_BASE + REG_SIZE * id, \
41 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
43 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
44 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
Dpinctrl-msm8909.c21 #define REG_SIZE 0x1000 macro
40 .ctl_reg = REG_SIZE * id, \
41 .io_reg = 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
43 .intr_status_reg = 0xc + REG_SIZE * id, \
44 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-qcm2290.c20 #define REG_SIZE 0x1000 macro
40 .ctl_reg = REG_SIZE * id, \
41 .io_reg = 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
43 .intr_status_reg = 0xc + REG_SIZE * id, \
44 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-msm8976.c23 #define REG_SIZE 0x1000 macro
42 .ctl_reg = REG_BASE + REG_SIZE * id, \
43 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
44 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
45 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
46 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
Dpinctrl-sdm660.c26 #define REG_SIZE 0x1000 macro
54 .ctl_reg = REG_SIZE * id, \
55 .io_reg = 0x4 + REG_SIZE * id, \
56 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
57 .intr_status_reg = 0xc + REG_SIZE * id, \
58 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-sm6350.c21 #define REG_SIZE 0x1000 macro
40 .ctl_reg = REG_SIZE * id, \
41 .io_reg = 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
43 .intr_status_reg = 0xc + REG_SIZE * id, \
44 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-sm6375.c22 #define REG_SIZE 0x1000 macro
41 .ctl_reg = REG_SIZE * id, \
42 .io_reg = REG_SIZE * id + 0x4, \
43 .intr_cfg_reg = REG_SIZE * id + 0x8, \
44 .intr_status_reg = REG_SIZE * id + 0xc, \
45 .intr_target_reg = REG_SIZE * id + 0x8, \
Dpinctrl-msm8996.c21 #define REG_SIZE 0x1000 macro
40 .ctl_reg = REG_BASE + REG_SIZE * id, \
41 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
43 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
44 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
Dpinctrl-sdm845.c24 #define REG_SIZE 0x1000 macro
44 .ctl_reg = base + REG_SIZE * id, \
45 .io_reg = base + 0x4 + REG_SIZE * id, \
46 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
47 .intr_status_reg = base + 0xc + REG_SIZE * id, \
48 .intr_target_reg = base + 0x8 + REG_SIZE * id, \
Dpinctrl-sm8250.c32 #define REG_SIZE 0x1000 macro
51 .ctl_reg = REG_SIZE * id, \
52 .io_reg = REG_SIZE * id + 0x4, \
53 .intr_cfg_reg = REG_SIZE * id + 0x8, \
54 .intr_status_reg = REG_SIZE * id + 0xc, \
55 .intr_target_reg = REG_SIZE * id + 0x8, \
Dpinctrl-sc8280xp.c21 #define REG_SIZE 0x1000 macro
38 .ctl_reg = REG_SIZE * id, \
39 .io_reg = 0x4 + REG_SIZE * id, \
40 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
41 .intr_status_reg = 0xc + REG_SIZE * id, \
42 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-sm8350.c21 #define REG_SIZE 0x1000 macro
41 .ctl_reg = REG_SIZE * id, \
42 .io_reg = REG_SIZE * id + 0x4, \
43 .intr_cfg_reg = REG_SIZE * id + 0x8, \
44 .intr_status_reg = REG_SIZE * id + 0xc, \
45 .intr_target_reg = REG_SIZE * id + 0x8, \
Dpinctrl-sm8450.c21 #define REG_SIZE 0x1000 macro
41 .ctl_reg = REG_SIZE * id, \
42 .io_reg = 0x4 + REG_SIZE * id, \
43 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
44 .intr_status_reg = 0xc + REG_SIZE * id, \
45 .intr_target_reg = 0x8 + REG_SIZE * id, \
Dpinctrl-sc8180x.c48 #define REG_SIZE 0x1000 macro
67 .ctl_reg = REG_SIZE * id + offset, \
68 .io_reg = REG_SIZE * id + 0x4 + offset, \
69 .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \
70 .intr_status_reg = REG_SIZE * id + 0xc + offset,\
71 .intr_target_reg = REG_SIZE * id + 0x8 + offset,\
/Linux-v6.1/drivers/net/ethernet/qlogic/qed/
Dqed_init_fw_funcs.c1430 #define REG_SIZE sizeof(u32) macro
1447 sizeof(ram_line) / REG_SIZE); in qed_gft_disable()
1565 sizeof(ram_line) / REG_SIZE); in qed_gft_config()
1573 sizeof(ram_line) / REG_SIZE); in qed_gft_config()