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Searched refs:REG_BASE (Results 1 – 9 of 9) sorted by relevance

/Linux-v6.1/arch/mips/n64/
Dinit.c53 #define REG_BASE ((u32 *) CKSEG1ADDR(0x4400000)) macro
57 __raw_writel(value, REG_BASE + reg); in n64rdp_write_reg()
60 #undef REG_BASE
/Linux-v6.1/drivers/pinctrl/qcom/
Dpinctrl-sdx65.c20 #define REG_BASE 0x0 macro
40 .ctl_reg = REG_BASE + REG_SIZE * id, \
41 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
43 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
44 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
Dpinctrl-msm8976.c22 #define REG_BASE 0x0 macro
42 .ctl_reg = REG_BASE + REG_SIZE * id, \
43 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
44 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
45 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
46 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
Dpinctrl-msm8996.c20 #define REG_BASE 0x0 macro
40 .ctl_reg = REG_BASE + REG_SIZE * id, \
41 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
43 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
44 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
Dpinctrl-sm6375.c21 #define REG_BASE 0x100000 macro
/Linux-v6.1/drivers/atm/
Dmidway.h23 #define REG_BASE 0x00040000 /* offset of Midway register area */ macro
Diphase.h632 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE macro
Deni.c1748 eni_dev->reg = base+REG_BASE; in eni_do_init()
Diphase.c2386 iadev->reg = base + REG_BASE;