Searched refs:RADEON_CP_CSQ_CNTL (Results 1 – 4 of 4) sorted by relevance
1214 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); in r100_cp_init()1257 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_cp_disable()2578 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_asic_reset()4003 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()4005 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_restore_sanity()
478 WREG32(RADEON_CP_CSQ_CNTL, 0); in rs600_asic_reset()
428 WREG32(RADEON_CP_CSQ_CNTL, 0); in r300_asic_reset()
3333 #define RADEON_CP_CSQ_CNTL 0x0740 macro
