Searched refs:Pixel (Results 1 – 25 of 34) sorted by relevance
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1 Freescale Pixel Pipeline4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
21 tristate "NXP i.MX Pixel Pipeline (PXP)"27 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
31 Bits Per Pixel34 * PCLK: Pixel Clock41 * PPLL: Pixel PLL
26 * **Output Pixel Processing (OPP)**: Process and format pixels to be sent to66 1. Pixel data interface (red): Represents the pixel data flow;
90 Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) argument
5 Pixel data transmitter and receiver drivers61 Pixel rate
4 Square Pixel for Color Cameras. It is programmable through I2C and 4-wire
15 Pixel Valve (DRM CRTC)
31 Pixel sampling rate in the device's pixel array. This control is
145 - IN: Pixel format for which the frame sizes are enumerated.
131 - IN: Pixel format for which the frame intervals are enumerated.
109 - Graphics content. Pixel data should be passed unfiltered and
396 Pixel format erratum.
116 - Pixel clock in Hz. Ex. 74.25MHz->74250000
55 The Pixel lightbar has a number of built-in sequences
34 imx-pxp i.MX Pixel Pipeline (PXP)
39 hardware blocks. The VFE has different input interfaces. The PIX (Pixel) input
16 Pixel Array sub-device
20 /* Pixel clock, porches, etc */
33 Pixel clock in picoseconds
124 Pixel values are encoded as indices into a colormap that stores red, green and268 Pixel values are bits_per_pixel wide and are split in non-overlapping red,
162 tristate "Chromebook Pixel's lightbar support"166 This option exposes the Chromebook Pixel's lightbar to
1713 #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ argument1714 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
