Searched refs:PLL4 (Results 1 – 15 of 15) sorted by relevance
| /Linux-v6.1/include/dt-bindings/clock/ |
| D | qcom,lcc-ipq806x.h | 9 #define PLL4 0 macro
|
| D | qcom,lcc-mdm9615.h | 11 #define PLL4 0 macro
|
| D | qcom,lcc-msm8960.h | 9 #define PLL4 0 macro
|
| D | stm32mp13-clks.h | 22 #define PLL4 9 macro
|
| D | stm32mp1-clks.h | 186 #define PLL4 179 macro
|
| /Linux-v6.1/arch/arm/boot/dts/ |
| D | stm32mp157c-odyssey.dts | 41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
|
| D | qcom-msm8960.dtsi | 136 <&lcc PLL4>;
|
| D | qcom-apq8064.dtsi | 821 <&lcc PLL4>;
|
| /Linux-v6.1/drivers/clk/qcom/ |
| D | lcc-ipq806x.c | 402 [PLL4] = &pll4.clkr,
|
| D | lcc-msm8960.c | 396 [PLL4] = &pll4.clkr,
|
| D | lcc-mdm9615.c | 481 [PLL4] = &pll4.clkr,
|
| /Linux-v6.1/drivers/net/wireless/ath/ath9k/ |
| D | reg.h | 1377 #define PLL4 0x1618c macro
|
| D | hw.c | 744 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
|
| /Linux-v6.1/arch/arm64/boot/dts/ti/ |
| D | k3-am65-main.dtsi | 853 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
|
| /Linux-v6.1/drivers/clk/ |
| D | clk-stm32mp1.c | 1776 PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
|
