Searched refs:PLL0_REFCLK (Results 1 – 2 of 2) sorted by relevance
62 PLL0_REFCLK, enumerator561 wiz->mux_sel_field[PLL0_REFCLK] = in wiz_regfield_init()563 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) { in wiz_regfield_init()565 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]); in wiz_regfield_init()
214 PLL0_REFCLK, enumerator278 [CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK },279 [CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK },1156 sp->input_clks[PLL0_REFCLK] = clk; in cdns_sierra_phy_get_clocks()
