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Searched refs:PIPE_A (Results 1 – 25 of 43) sorted by relevance

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/Linux-v6.1/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c114 MMIO_D(PIPEDSL(PIPE_A)); in iterate_generic_mmio()
118 MMIO_D(PIPECONF(PIPE_A)); in iterate_generic_mmio()
122 MMIO_D(PIPESTAT(PIPE_A)); in iterate_generic_mmio()
126 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A)); in iterate_generic_mmio()
130 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A)); in iterate_generic_mmio()
134 MMIO_D(CURCNTR(PIPE_A)); in iterate_generic_mmio()
137 MMIO_D(CURPOS(PIPE_A)); in iterate_generic_mmio()
140 MMIO_D(CURBASE(PIPE_A)); in iterate_generic_mmio()
143 MMIO_D(CUR_FBC_CTL(PIPE_A)); in iterate_generic_mmio()
153 MMIO_D(DSPCNTR(PIPE_A)); in iterate_generic_mmio()
[all …]
Di915_pci.c104 [PIPE_A] = CURSOR_A_OFFSET, \
109 [PIPE_A] = CURSOR_A_OFFSET, \
115 [PIPE_A] = CURSOR_A_OFFSET, \
122 [PIPE_A] = CURSOR_A_OFFSET, \
129 [PIPE_A] = CURSOR_A_OFFSET, \
176 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
198 .__runtime.pipe_mask = BIT(PIPE_A), \
241 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
332 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
386 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
[all …]
Dintel_pm.c473 case PIPE_A: in vlv_get_fifo_size()
957 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
963 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
964 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
1007 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
1009 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
1010 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1011 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1033 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1034 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Dintel_device_info.c321 runtime->num_scalers[PIPE_A] = 2; in intel_device_info_runtime_init()
347 runtime->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
390 runtime->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
Di915_irq.c617 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1459 case PIPE_A: in i9xx_pipestat_irq_ack()
1894 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
2412 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
3041 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
3962 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4141 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4261 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
4262 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_fdi.c162 case PIPE_A: in ilk_check_fdi_lanes()
313 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
788 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
795 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
796 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
801 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
828 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
832 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
833 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
839 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
Dintel_pch_display.c21 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
29 return PIPE_A; in intel_crtc_pch_transcoder()
114 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
122 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
133 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
141 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()
556 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
558 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
564 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
593 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
[all …]
Dskl_watermark.c818 .active_pipes = BIT(PIPE_A),
820 [PIPE_A] = BIT(DBUF_S1),
830 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
832 [PIPE_A] = BIT(DBUF_S1),
843 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
845 [PIPE_A] = BIT(DBUF_S1),
857 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
859 [PIPE_A] = BIT(DBUF_S1),
881 .active_pipes = BIT(PIPE_A),
883 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
[all …]
Dintel_cursor.c283 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); in i845_cursor_update_arm()
284 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); in i845_cursor_update_arm()
285 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); in i845_cursor_update_arm()
286 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
287 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); in i845_cursor_update_arm()
293 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); in i845_cursor_update_arm()
311 power_domain = POWER_DOMAIN_PIPE(PIPE_A); in i845_cursor_get_hw_state()
316 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
318 *pipe = PIPE_A; in i845_cursor_get_hw_state()
Dg4x_hdmi.c315 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
316 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
319 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
333 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
334 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
335 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
584 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
Dintel_display_trace.h42 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
69 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
166 __entry->frame[PIPE_A], __entry->scanline[PIPE_A],
Dg4x_dp.c269 *pipe = PIPE_A; in cpt_dp_port_selected()
443 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
444 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
448 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
457 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
458 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
459 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
1366 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
Dintel_crt.c242 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
271 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
283 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
328 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1049 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1115 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Dintel_display_power_well.c1035 if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1036 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
1045 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
1051 return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1194 if (pipe != PIPE_A) in vlv_display_power_well_init()
1418 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1483 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1509 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1638 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1669 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
Dintel_pipe_crc.c180 case PIPE_A: in vlv_pipe_crc_ctl_reg()
244 case PIPE_A: in vlv_undo_pipe_scramble_reset()
317 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
Dintel_fifo_underrun.c136 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
223 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
Dhsw_ips.c179 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
Dintel_dpll.c1185 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
1203 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
1687 if (pipe == PIPE_A) in vlv_prepare_pll()
1695 if (pipe == PIPE_A) in vlv_prepare_pll()
1900 if (pipe != PIPE_A) { in chv_enable_pll()
1974 if (pipe != PIPE_A) in vlv_disable_pll()
1991 if (pipe != PIPE_A) in chv_disable_pll()
Dintel_display.h90 PIPE_A = 0, enumerator
109 TRANSCODER_A = PIPE_A,
Dintel_pps.c128 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
185 pipe = PIPE_A; in vlv_power_sequencer_pipe()
263 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
966 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
/Linux-v6.1/drivers/gpu/drm/i915/gvt/
Dhandlers.c687 vgpu->id, pipe_name(PIPE_A), new_rate); in vgpu_update_refresh_rate()
2264 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2268 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2269 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2277 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2278 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2303 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); in init_generic_mmio_info()
2306 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2309 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2456 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
[all …]
Dreg.h71 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
81 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
Ddisplay.c47 pipe = PIPE_A; in get_edp_pipe()
76 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
249 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE; in emulate_monitor_status_change()
506 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
624 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
630 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
/Linux-v6.1/drivers/video/fbdev/intelfb/
Dintelfbhw.c480 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()
481 return PIPE_A; in intelfbhw_active_pipe()
486 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()
487 return PIPE_A; in intelfbhw_active_pipe()
492 pipe = PIPE_A; in intelfbhw_active_pipe()
501 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
Dintelfbhw.h182 #define PIPE_A 0 macro

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