Searched refs:PIPECONF_INTERLACE_MASK (Results 1 – 4 of 4) sorted by relevance
297 #define PIPECONF_INTERLACE_MASK (7 << 21) macro
1269 *pipe_conf &= ~PIPECONF_INTERLACE_MASK; in intelfbhw_mode_to_hw()
3594 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ macro3595 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)3596 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 …3597 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */3598 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)3599 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
2940 return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; in intel_pipe_is_interlaced()
