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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 25 of 34) sorted by relevance

12

/Linux-v6.1/drivers/pinctrl/renesas/
Dpfc-sh7722.c1258 { PINMUX_CFG_REG_VAR("PCCR", 0xa4050104, 16,
1280 { PINMUX_CFG_REG_VAR("PECR", 0xa4050108, 16,
1301 { PINMUX_CFG_REG_VAR("PGCR", 0xa405010c, 16,
1321 { PINMUX_CFG_REG_VAR("PJCR", 0xa4050110, 16,
1381 { PINMUX_CFG_REG_VAR("PRCR", 0xa405011c, 16,
1391 { PINMUX_CFG_REG_VAR("PSCR", 0xa405011e, 16,
1401 { PINMUX_CFG_REG_VAR("PTCR", 0xa4050140, 16,
1411 { PINMUX_CFG_REG_VAR("PUCR", 0xa4050142, 16,
1421 { PINMUX_CFG_REG_VAR("PVCR", 0xa4050144, 16,
1451 { PINMUX_CFG_REG_VAR("PYCR", 0xa405014a, 16,
[all …]
Dpfc-r8a7792.c2002 { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
2099 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32,
2122 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32,
2145 { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32,
2168 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32,
2191 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32,
2214 { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32,
2305 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2361 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2414 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
[all …]
Dpfc-sh7264.c1467 { PINMUX_CFG_REG_VAR("PAIOR0", 0xfffe3812, 16,
1477 { PINMUX_CFG_REG_VAR("PBCR5", 0xfffe3824, 16,
1529 { PINMUX_CFG_REG_VAR("PBCR0", 0xfffe382e, 16,
1541 { PINMUX_CFG_REG_VAR("PBIOR1", 0xfffe3830, 16,
1573 { PINMUX_CFG_REG_VAR("PCCR2", 0xfffe384a, 16,
1605 { PINMUX_CFG_REG_VAR("PCIOR0", 0xfffe3852, 16,
1683 { PINMUX_CFG_REG_VAR("PECR1", 0xfffe388c, 16,
1705 { PINMUX_CFG_REG_VAR("PEIOR0", 0xfffe3892, 16,
1717 { PINMUX_CFG_REG_VAR("PFCR3", 0xfffe38a8, 16,
1787 { PINMUX_CFG_REG_VAR("PGCR7", 0xfffe38c0, 16,
[all …]
Dpfc-sh7734.c1808 { PINMUX_CFG_REG_VAR("GPSR5", 0xFFFC0018, 32,
1821 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1858 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1894 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1930 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1967 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2003 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2035 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2064 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2100 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
[all …]
Dpfc-sh7720.c1017 { PINMUX_CFG_REG_VAR("PKCR", 0xa4050112, 16,
1026 { PINMUX_CFG_REG_VAR("PLCR", 0xa4050114, 16,
1046 { PINMUX_CFG_REG_VAR("PPCR", 0xa4050118, 16,
1066 { PINMUX_CFG_REG_VAR("PSCR", 0xa405011c, 16,
1076 { PINMUX_CFG_REG_VAR("PTCR", 0xa405011e, 16,
1086 { PINMUX_CFG_REG_VAR("PUCR", 0xa4050120, 16,
1096 { PINMUX_CFG_REG_VAR("PVCR", 0xa4050122, 16,
Dpfc-emev2.c1571 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1585 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1593 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1601 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1623 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1639 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
Dpfc-r8a7779.c3303 { PINMUX_CFG_REG_VAR("GPSR6", 0xfffc001c, 32,
3318 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3356 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3394 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3440 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3492 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3541 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3587 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3624 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3661 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
[all …]
Dpfc-r8a779g0.c3025 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3084 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3178 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3205 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3232 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3259 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3304 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3342 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3372 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3411 { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
[all …]
Dpfc-r8a7790.c5124 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5160 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5197 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5226 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5260 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5293 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5329 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5365 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5400 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5441 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7778.c2242 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2297 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2339 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2392 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2435 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2478 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2523 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2575 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2615 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2653 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7794.c4868 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4910 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4950 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4986 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5028 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5064 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5101 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5148 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5185 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5221 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7791.c5688 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5747 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5784 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5820 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5858 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5902 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5941 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5981 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6022 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6065 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-sh7785.c1027 { PINMUX_CFG_REG_VAR("PECR", 0xffe70008, 16,
1098 { PINMUX_CFG_REG_VAR("PMCR", 0xffe70016, 16,
1115 { PINMUX_CFG_REG_VAR("PPCR", 0xffe7001a, 16,
1126 { PINMUX_CFG_REG_VAR("PQCR", 0xffe7001c, 16,
1136 { PINMUX_CFG_REG_VAR("PRCR", 0xffe7001e, 16,
1163 { PINMUX_CFG_REG_VAR("P2MSELR", 0xffe70082, 16,
Dpfc-sh7723.c1549 { PINMUX_CFG_REG_VAR("PECR", 0xa4050108, 16,
1570 { PINMUX_CFG_REG_VAR("PGCR", 0xa405010c, 16,
1591 { PINMUX_CFG_REG_VAR("PJCR", 0xa4050110, 16,
1643 { PINMUX_CFG_REG_VAR("PQCR", 0xa405011a, 16,
1672 { PINMUX_CFG_REG_VAR("PTCR", 0xa4050140, 16,
1683 { PINMUX_CFG_REG_VAR("PUCR", 0xa4050142, 16,
1744 { PINMUX_CFG_REG_VAR("PSELA", 0xa405014e, 16,
1755 { PINMUX_CFG_REG_VAR("PSELB", 0xa4050150, 16,
1767 { PINMUX_CFG_REG_VAR("PSELC", 0xa4050152, 16,
Dpfc-r8a779f0.c1620 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6050040, 32,
1647 { PINMUX_CFG_REG_VAR("GPSR1", 0xe6050840, 32,
1678 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6051040, 32,
1701 { PINMUX_CFG_REG_VAR("GPSR3", 0xe6051840, 32,
1751 { PINMUX_CFG_REG_VAR("IP2SR0", 0xe6050068, 32,
1776 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32,
Dpfc-sh7269.c1969 { PINMUX_CFG_REG_VAR("PAIOR0", 0xfffe3812, 16,
1977 { PINMUX_CFG_REG_VAR("PBCR5", 0xfffe3824, 16,
2051 { PINMUX_CFG_REG_VAR("PBCR0", 0xfffe382e, 16,
2066 { PINMUX_CFG_REG_VAR("PBIOR1", 0xfffe3830, 16,
2097 { PINMUX_CFG_REG_VAR("PCCR2", 0xfffe384a, 16,
2135 { PINMUX_CFG_REG_VAR("PCIOR0", 0xfffe3852, 16,
2251 { PINMUX_CFG_REG_VAR("PEIOR0", 0xfffe3892, 16,
2299 { PINMUX_CFG_REG_VAR("PFCR4", 0xfffe38a6, 16,
2307 { PINMUX_CFG_REG_VAR("PFCR3", 0xfffe38a8, 16,
2375 { PINMUX_CFG_REG_VAR("PFIOR1", 0xfffe38b0, 16,
Dpfc-r8a779a0.c3241 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32,
3272 { PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32,
3329 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32,
3356 { PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32,
3383 { PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32,
3410 { PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32,
3437 { PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32,
3499 { PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32,
3541 { PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32,
3552 { PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32,
[all …]
Dpfc-r8a77970.c2086 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2148 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
2171 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2194 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2205 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2311 { PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32,
2328 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Dpfc-sh7203.c1075 { PINMUX_CFG_REG_VAR("PBIORL", 0xfffe3886, 16,
1085 { PINMUX_CFG_REG_VAR("PBCRL4", 0xfffe3890, 16,
1131 { PINMUX_CFG_REG_VAR("IFCR", 0xfffe38a2, 16,
1156 { PINMUX_CFG_REG_VAR("PCCRL4", 0xfffe3910, 16,
1407 { PINMUX_CFG_REG_VAR("PFCRH4", 0xfffe3a88, 16,
Dpfc-sh7757.c1966 { PINMUX_CFG_REG_VAR("PSEL1", 0xffec0072, 16,
1977 { PINMUX_CFG_REG_VAR("PSEL2", 0xffec0074, 16,
1992 { PINMUX_CFG_REG_VAR("PSEL3", 0xffec0076, 16,
2010 { PINMUX_CFG_REG_VAR("PSEL4", 0xffec0078, 16,
2029 { PINMUX_CFG_REG_VAR("PSEL5", 0xffec007a, 16,
2063 { PINMUX_CFG_REG_VAR("PSEL7", 0xffec0082, 16,
2079 { PINMUX_CFG_REG_VAR("PSEL8", 0xffec0084, 16,
Dpfc-r8a77470.c2488 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6060004, 32,
2517 { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32,
2580 { PINMUX_CFG_REG_VAR("GPSR3", 0xE6060010, 32,
3125 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3151 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3185 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3228 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
Dpfc-r8a77995.c2489 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2571 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2620 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2647 { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
2802 { PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
2814 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2844 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Dsh_pfc.h151 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ macro
747 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(-2, 2, -1, 3), \
Dpfc-r8a77980.c2507 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2603 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2626 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2658 { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2784 { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2799 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Dpfc-sh7786.c669 { PINMUX_CFG_REG_VAR("PECR", 0xffcc0008, 16,
686 { PINMUX_CFG_REG_VAR("PGCR", 0xffcc000c, 16,

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