Searched refs:PACKET3_SET_UCONFIG_REG_START (Results 1 – 11 of 11) sorted by relevance
298 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
336 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
352 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
470 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
2075 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v7_0_ring_test_ring()2340 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START; in gfx_v7_0_ring_test_ib()
1003 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); in gfx_v9_0_ring_test_ring()3107 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); in gfx_v9_0_cp_gfx_start()
328 PACKET3_SET_UCONFIG_REG_START); in gfx_v11_0_ring_test_ring()
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v8_0_ring_test_ring()
3798 PACKET3_SET_UCONFIG_REG_START); in gfx_v10_0_ring_test_ring()
1938 #define PACKET3_SET_UCONFIG_REG_START 0x00030000 macro
3465 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()3737 PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_ib_execute()3790 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2); in cik_ib_test()
