Searched refs:NumDispClkLevelsEnabled (Results 1 – 13 of 13) sorted by relevance
583 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()584 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn31_clk_mgr_helper_populate_bw_params()585 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()586 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()758 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn31_clk_mgr_construct()769 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn31_clk_mgr_construct()
141 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
591 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()592 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params()593 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()594 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()807 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn314_clk_mgr_construct()818 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn314_clk_mgr_construct()
60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
520 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn316_clk_mgr_helper_populate_bw_params()521 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn316_clk_mgr_helper_populate_bw_params()522 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()523 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
121 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
132 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
79 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
691 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn315_clk_mgr_construct()702 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn315_clk_mgr_construct()
116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
