Searched refs:MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 (Results 1 – 14 of 14) sorted by relevance
22 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */
379 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */519 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0
329 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
427 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099
752 #define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 macro
177 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */
500 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
561 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
129 #define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 macro
275 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b088 /* FPGA_RESET */
705 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0
625 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */
730 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1
528 fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;