Searched refs:MSR_IA32_APICBASE_ENABLE (Results 1 – 8 of 8) sorted by relevance
14 ~(MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD)); in apic_disable()25 rdmsr(MSR_IA32_APICBASE) | MSR_IA32_APICBASE_ENABLE); in xapic_enable()26 } else if (!(val & MSR_IA32_APICBASE_ENABLE)) { in xapic_enable()27 wrmsr(MSR_IA32_APICBASE, val | MSR_IA32_APICBASE_ENABLE); in xapic_enable()42 MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD); in x2apic_enable()
28 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,29 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,194 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; in kvm_apic_hw_enabled()195 return MSR_IA32_APICBASE_ENABLE; in kvm_apic_hw_enabled()269 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); in kvm_apic_mode()
2318 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) in kvm_free_lapic()2378 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) in kvm_lapic_set_base()2385 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { in kvm_lapic_set_base()2386 if (value & MSR_IA32_APICBASE_ENABLE) { in kvm_lapic_set_base()2400 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) { in kvm_lapic_set_base()2408 if ((value & MSR_IA32_APICBASE_ENABLE) && in kvm_lapic_set_base()2442 msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; in kvm_lapic_reset()2607 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; in kvm_create_lapic()
262 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); in __kvm_update_cpuid_runtime()
21 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro
1241 l &= ~MSR_IA32_APICBASE_ENABLE; in disable_local_APIC()2023 if (l & MSR_IA32_APICBASE_ENABLE) in apic_verify()2045 if (!(l & MSR_IA32_APICBASE_ENABLE)) { in apic_force_enable()2048 l |= MSR_IA32_APICBASE_ENABLE | addr; in apic_force_enable()2776 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; in lapic_resume()
746 #define MSR_IA32_APICBASE_ENABLE (1<<11) macro
