Searched refs:MPLL_FREQ_LEVEL_0 (Results 1 – 2 of 2) sorted by relevance
78 #define MPLL_FREQ_LEVEL_0 0x6e8 macro
373 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_enable_post_divider()376 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); in rv6xx_memory_clock_entry_enable_post_divider()382 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_post_divider()389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), in rv6xx_memory_clock_entry_set_feedback_divider()396 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_reference_divider()
