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Searched refs:MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT (Results 1 – 13 of 13) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_sh_mask.h11076 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_1_0_sh_mask.h20466 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_1_sh_mask.h15293 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_1_sh_mask.h40312 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_1_0_sh_mask.h19113 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_5_sh_mask.h20791 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_2_sh_mask.h22774 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_2_sh_mask.h47314 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_6_sh_mask.h23532 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_4_sh_mask.h55997 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_0_sh_mask.h54463 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_0_0_sh_mask.h23534 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_0_sh_mask.h15290 #define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro