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Searched refs:MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT (Results 1 – 13 of 13) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_sh_mask.h10982 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_1_0_sh_mask.h20370 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_1_sh_mask.h15205 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_1_sh_mask.h40229 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_1_0_sh_mask.h19010 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_5_sh_mask.h20708 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_2_sh_mask.h22691 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_2_sh_mask.h47231 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_6_sh_mask.h23449 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_4_sh_mask.h55914 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_0_sh_mask.h54381 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_0_0_sh_mask.h23438 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_0_sh_mask.h15202 #define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro