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Searched refs:MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT (Results 1 – 14 of 14) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_sh_mask.h10888 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_3_sh_mask.h24195 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_1_0_sh_mask.h20274 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_1_sh_mask.h15117 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_1_sh_mask.h40146 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_1_0_sh_mask.h18907 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_5_sh_mask.h20625 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_2_sh_mask.h22608 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_2_sh_mask.h47148 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_6_sh_mask.h23366 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_1_4_sh_mask.h55831 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_0_0_sh_mask.h54298 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_2_0_0_sh_mask.h23342 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
Ddcn_3_2_0_sh_mask.h15114 #define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro