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Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 25 of 34) sorted by relevance

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/Linux-v6.1/drivers/mmc/host/
Dsdhci-of-arasan.c659 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sdcardclk_set_phase()
728 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sampleclk_set_phase()
788 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sdcardclk_set_phase()
855 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sampleclk_set_phase()
927 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()
1124 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, in arasan_dt_parse_clk_phases()
Ddw_mmc-hi3798cv200.c33 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
Dsdhci-pxav3.c268 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()
281 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
Dsdhci-xenon.c214 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()
359 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
Dsdhci-xenon-phy.c620 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()
754 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
Drtsx_pci_sdmmc.c1036 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1117 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
1337 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()
1352 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
Dsdhci-pci-arasan.c284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
Dsdhci-st.c291 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
Dsdhci-brcmstb.c118 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_brcmstb_set_uhs_signaling()
Dsdhci-esdhc-imx.c1023 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
1133 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()
1258 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
Dusdhi6rol0.c750 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()
853 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()
860 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
Dsdhci-omap.c831 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()
1154 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
Dsdhci-of-dwcmshc.c170 else if ((timing == MMC_TIMING_UHS_DDR50) || in dwcmshc_set_uhs_signaling()
Ddw_mmc-exynos.c335 case MMC_TIMING_UHS_DDR50: in dw_mci_exynos_set_ios()
Dmmci_stm32_sdmmc.c254 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) in mmci_sdmmc_set_clkreg()
Dowl-mmc.c523 if (ios->timing == MMC_TIMING_UHS_DDR50) { in owl_mmc_set_ios()
Dsdhci-sprd.c344 case MMC_TIMING_UHS_DDR50: in sdhci_sprd_set_uhs_signaling()
Drtsx_usb_sdmmc.c1060 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1124 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
Dsunxi-mmc.c741 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()
891 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
Dsdhci_am654.c127 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
Dsdhci.c1880 case MMC_TIMING_UHS_DDR50: in sdhci_get_preset_value()
2288 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()
2304 case MMC_TIMING_UHS_DDR50: in sdhci_timing_has_preset()
2411 ios->timing == MMC_TIMING_UHS_DDR50 || in sdhci_set_ios()
2937 case MMC_TIMING_UHS_DDR50: in sdhci_execute_tuning()
/Linux-v6.1/include/linux/mmc/
Dhost.h60 #define MMC_TIMING_UHS_DDR50 7 macro
627 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
/Linux-v6.1/drivers/mmc/core/
Ddebugfs.c141 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
Dsd.c497 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()
669 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()
680 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
Dhost.c257 &map->phase[MMC_TIMING_UHS_DDR50]); in mmc_of_parse_clk_phase()

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