1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Atmel MACB Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7 #ifndef _MACB_H
8 #define _MACB_H
9
10 #include <linux/clk.h>
11 #include <linux/phylink.h>
12 #include <linux/ptp_clock_kernel.h>
13 #include <linux/net_tstamp.h>
14 #include <linux/interrupt.h>
15 #include <linux/phy/phy.h>
16
17 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
18 #define MACB_EXT_DESC
19 #endif
20
21 #define MACB_GREGS_NBR 16
22 #define MACB_GREGS_VERSION 2
23 #define MACB_MAX_QUEUES 8
24
25 /* MACB register offsets */
26 #define MACB_NCR 0x0000 /* Network Control */
27 #define MACB_NCFGR 0x0004 /* Network Config */
28 #define MACB_NSR 0x0008 /* Network Status */
29 #define MACB_TAR 0x000c /* AT91RM9200 only */
30 #define MACB_TCR 0x0010 /* AT91RM9200 only */
31 #define MACB_TSR 0x0014 /* Transmit Status */
32 #define MACB_RBQP 0x0018 /* RX Q Base Address */
33 #define MACB_TBQP 0x001c /* TX Q Base Address */
34 #define MACB_RSR 0x0020 /* Receive Status */
35 #define MACB_ISR 0x0024 /* Interrupt Status */
36 #define MACB_IER 0x0028 /* Interrupt Enable */
37 #define MACB_IDR 0x002c /* Interrupt Disable */
38 #define MACB_IMR 0x0030 /* Interrupt Mask */
39 #define MACB_MAN 0x0034 /* PHY Maintenance */
40 #define MACB_PTR 0x0038
41 #define MACB_PFR 0x003c
42 #define MACB_FTO 0x0040
43 #define MACB_SCF 0x0044
44 #define MACB_MCF 0x0048
45 #define MACB_FRO 0x004c
46 #define MACB_FCSE 0x0050
47 #define MACB_ALE 0x0054
48 #define MACB_DTF 0x0058
49 #define MACB_LCOL 0x005c
50 #define MACB_EXCOL 0x0060
51 #define MACB_TUND 0x0064
52 #define MACB_CSE 0x0068
53 #define MACB_RRE 0x006c
54 #define MACB_ROVR 0x0070
55 #define MACB_RSE 0x0074
56 #define MACB_ELE 0x0078
57 #define MACB_RJA 0x007c
58 #define MACB_USF 0x0080
59 #define MACB_STE 0x0084
60 #define MACB_RLE 0x0088
61 #define MACB_TPF 0x008c
62 #define MACB_HRB 0x0090
63 #define MACB_HRT 0x0094
64 #define MACB_SA1B 0x0098
65 #define MACB_SA1T 0x009c
66 #define MACB_SA2B 0x00a0
67 #define MACB_SA2T 0x00a4
68 #define MACB_SA3B 0x00a8
69 #define MACB_SA3T 0x00ac
70 #define MACB_SA4B 0x00b0
71 #define MACB_SA4T 0x00b4
72 #define MACB_TID 0x00b8
73 #define MACB_TPQ 0x00bc
74 #define MACB_USRIO 0x00c0
75 #define MACB_WOL 0x00c4
76 #define MACB_MID 0x00fc
77 #define MACB_TBQPH 0x04C8
78 #define MACB_RBQPH 0x04D4
79
80 /* GEM register offsets. */
81 #define GEM_NCR 0x0000 /* Network Control */
82 #define GEM_NCFGR 0x0004 /* Network Config */
83 #define GEM_USRIO 0x000c /* User IO */
84 #define GEM_DMACFG 0x0010 /* DMA Configuration */
85 #define GEM_JML 0x0048 /* Jumbo Max Length */
86 #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */
87 #define GEM_HRB 0x0080 /* Hash Bottom */
88 #define GEM_HRT 0x0084 /* Hash Top */
89 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
90 #define GEM_SA1T 0x008C /* Specific1 Top */
91 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
92 #define GEM_SA2T 0x0094 /* Specific2 Top */
93 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
94 #define GEM_SA3T 0x009C /* Specific3 Top */
95 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
96 #define GEM_SA4T 0x00A4 /* Specific4 Top */
97 #define GEM_WOL 0x00b8 /* Wake on LAN */
98 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
99 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
100 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
101 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
102 #define GEM_OTX 0x0100 /* Octets transmitted */
103 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
104 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
105 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
106 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
107 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
108 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
109 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
110 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
111 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
112 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
113 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
114 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
115 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
116 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
117 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
118 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
119 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
120 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
121 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
122 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
123 #define GEM_ORX 0x0150 /* Octets received */
124 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
125 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
126 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
127 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
128 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
129 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
130 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
131 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
132 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
133 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
134 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
135 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
136 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
137 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
138 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
139 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
140 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
141 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
142 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
143 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
144 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
145 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
146 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
147 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
148 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
149 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
150 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
151 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
152 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
153 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
154 #define GEM_TI 0x01dc /* 1588 Timer Increment */
155 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
156 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
157 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
158 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
159 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
160 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
161 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
162 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
163 #define GEM_PCSCNTRL 0x0200 /* PCS Control */
164 #define GEM_PCSSTS 0x0204 /* PCS Status */
165 #define GEM_PCSPHYTOPID 0x0208 /* PCS PHY Top ID */
166 #define GEM_PCSPHYBOTID 0x020c /* PCS PHY Bottom ID */
167 #define GEM_PCSANADV 0x0210 /* PCS AN Advertisement */
168 #define GEM_PCSANLPBASE 0x0214 /* PCS AN Link Partner Base */
169 #define GEM_PCSANEXP 0x0218 /* PCS AN Expansion */
170 #define GEM_PCSANNPTX 0x021c /* PCS AN Next Page TX */
171 #define GEM_PCSANNPLP 0x0220 /* PCS AN Next Page LP */
172 #define GEM_PCSANEXTSTS 0x023c /* PCS AN Extended Status */
173 #define GEM_DCFG1 0x0280 /* Design Config 1 */
174 #define GEM_DCFG2 0x0284 /* Design Config 2 */
175 #define GEM_DCFG3 0x0288 /* Design Config 3 */
176 #define GEM_DCFG4 0x028c /* Design Config 4 */
177 #define GEM_DCFG5 0x0290 /* Design Config 5 */
178 #define GEM_DCFG6 0x0294 /* Design Config 6 */
179 #define GEM_DCFG7 0x0298 /* Design Config 7 */
180 #define GEM_DCFG8 0x029C /* Design Config 8 */
181 #define GEM_DCFG10 0x02A4 /* Design Config 10 */
182 #define GEM_DCFG12 0x02AC /* Design Config 12 */
183 #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */
184 #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */
185
186 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
187 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
188
189 /* Screener Type 2 match registers */
190 #define GEM_SCRT2 0x540
191
192 /* EtherType registers */
193 #define GEM_ETHT 0x06E0
194
195 /* Type 2 compare registers */
196 #define GEM_T2CMPW0 0x0700
197 #define GEM_T2CMPW1 0x0704
198 #define T2CMP_OFST(t2idx) (t2idx * 2)
199
200 /* type 2 compare registers
201 * each location requires 3 compare regs
202 */
203 #define GEM_IP4SRC_CMP(idx) (idx * 3)
204 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
205 #define GEM_PORT_CMP(idx) (idx * 3 + 2)
206
207 /* Which screening type 2 EtherType register will be used (0 - 7) */
208 #define SCRT2_ETHT 0
209
210 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
211 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
212 #define GEM_TBQPH(hw_q) (0x04C8)
213 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
214 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
215 #define GEM_RBQPH(hw_q) (0x04D4)
216 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
217 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
218 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
219
220 /* Bitfields in NCR */
221 #define MACB_LB_OFFSET 0 /* reserved */
222 #define MACB_LB_SIZE 1
223 #define MACB_LLB_OFFSET 1 /* Loop back local */
224 #define MACB_LLB_SIZE 1
225 #define MACB_RE_OFFSET 2 /* Receive enable */
226 #define MACB_RE_SIZE 1
227 #define MACB_TE_OFFSET 3 /* Transmit enable */
228 #define MACB_TE_SIZE 1
229 #define MACB_MPE_OFFSET 4 /* Management port enable */
230 #define MACB_MPE_SIZE 1
231 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
232 #define MACB_CLRSTAT_SIZE 1
233 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
234 #define MACB_INCSTAT_SIZE 1
235 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
236 #define MACB_WESTAT_SIZE 1
237 #define MACB_BP_OFFSET 8 /* Back pressure */
238 #define MACB_BP_SIZE 1
239 #define MACB_TSTART_OFFSET 9 /* Start transmission */
240 #define MACB_TSTART_SIZE 1
241 #define MACB_THALT_OFFSET 10 /* Transmit halt */
242 #define MACB_THALT_SIZE 1
243 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
244 #define MACB_NCR_TPF_SIZE 1
245 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
246 #define MACB_TZQ_SIZE 1
247 #define MACB_SRTSM_OFFSET 15 /* Store Receive Timestamp to Memory */
248 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
249 #define MACB_OSSMODE_SIZE 1
250 #define MACB_MIIONRGMII_OFFSET 28 /* MII Usage on RGMII Interface */
251 #define MACB_MIIONRGMII_SIZE 1
252
253 /* Bitfields in NCFGR */
254 #define MACB_SPD_OFFSET 0 /* Speed */
255 #define MACB_SPD_SIZE 1
256 #define MACB_FD_OFFSET 1 /* Full duplex */
257 #define MACB_FD_SIZE 1
258 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
259 #define MACB_BIT_RATE_SIZE 1
260 #define MACB_JFRAME_OFFSET 3 /* reserved */
261 #define MACB_JFRAME_SIZE 1
262 #define MACB_CAF_OFFSET 4 /* Copy all frames */
263 #define MACB_CAF_SIZE 1
264 #define MACB_NBC_OFFSET 5 /* No broadcast */
265 #define MACB_NBC_SIZE 1
266 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
267 #define MACB_NCFGR_MTI_SIZE 1
268 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
269 #define MACB_UNI_SIZE 1
270 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
271 #define MACB_BIG_SIZE 1
272 #define MACB_EAE_OFFSET 9 /* External address match enable */
273 #define MACB_EAE_SIZE 1
274 #define MACB_CLK_OFFSET 10
275 #define MACB_CLK_SIZE 2
276 #define MACB_RTY_OFFSET 12 /* Retry test */
277 #define MACB_RTY_SIZE 1
278 #define MACB_PAE_OFFSET 13 /* Pause enable */
279 #define MACB_PAE_SIZE 1
280 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
281 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
282 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
283 #define MACB_RBOF_SIZE 2
284 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
285 #define MACB_RLCE_SIZE 1
286 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
287 #define MACB_DRFCS_SIZE 1
288 #define MACB_EFRHD_OFFSET 18
289 #define MACB_EFRHD_SIZE 1
290 #define MACB_IRXFCS_OFFSET 19
291 #define MACB_IRXFCS_SIZE 1
292
293 /* GEM specific NCR bitfields. */
294 #define GEM_ENABLE_HS_MAC_OFFSET 31
295 #define GEM_ENABLE_HS_MAC_SIZE 1
296
297 /* GEM specific NCFGR bitfields. */
298 #define GEM_FD_OFFSET 1 /* Full duplex */
299 #define GEM_FD_SIZE 1
300 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
301 #define GEM_GBE_SIZE 1
302 #define GEM_PCSSEL_OFFSET 11
303 #define GEM_PCSSEL_SIZE 1
304 #define GEM_PAE_OFFSET 13 /* Pause enable */
305 #define GEM_PAE_SIZE 1
306 #define GEM_CLK_OFFSET 18 /* MDC clock division */
307 #define GEM_CLK_SIZE 3
308 #define GEM_DBW_OFFSET 21 /* Data bus width */
309 #define GEM_DBW_SIZE 2
310 #define GEM_RXCOEN_OFFSET 24
311 #define GEM_RXCOEN_SIZE 1
312 #define GEM_SGMIIEN_OFFSET 27
313 #define GEM_SGMIIEN_SIZE 1
314
315
316 /* Constants for data bus width. */
317 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
318 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
319 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
320
321 /* Bitfields in DMACFG. */
322 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
323 #define GEM_FBLDO_SIZE 5
324 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
325 #define GEM_ENDIA_DESC_SIZE 1
326 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
327 #define GEM_ENDIA_PKT_SIZE 1
328 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
329 #define GEM_RXBMS_SIZE 2
330 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
331 #define GEM_TXPBMS_SIZE 1
332 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
333 #define GEM_TXCOEN_SIZE 1
334 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
335 #define GEM_RXBS_SIZE 8
336 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
337 #define GEM_DDRP_SIZE 1
338 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
339 #define GEM_RXEXT_SIZE 1
340 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
341 #define GEM_TXEXT_SIZE 1
342 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
343 #define GEM_ADDR64_SIZE 1
344
345
346 /* Bitfields in NSR */
347 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
348 #define MACB_NSR_LINK_SIZE 1
349 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
350 #define MACB_MDIO_SIZE 1
351 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
352 #define MACB_IDLE_SIZE 1
353
354 /* Bitfields in TSR */
355 #define MACB_UBR_OFFSET 0 /* Used bit read */
356 #define MACB_UBR_SIZE 1
357 #define MACB_COL_OFFSET 1 /* Collision occurred */
358 #define MACB_COL_SIZE 1
359 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
360 #define MACB_TSR_RLE_SIZE 1
361 #define MACB_TGO_OFFSET 3 /* Transmit go */
362 #define MACB_TGO_SIZE 1
363 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
364 #define MACB_BEX_SIZE 1
365 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
366 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
367 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
368 #define MACB_COMP_SIZE 1
369 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
370 #define MACB_UND_SIZE 1
371
372 /* Bitfields in RSR */
373 #define MACB_BNA_OFFSET 0 /* Buffer not available */
374 #define MACB_BNA_SIZE 1
375 #define MACB_REC_OFFSET 1 /* Frame received */
376 #define MACB_REC_SIZE 1
377 #define MACB_OVR_OFFSET 2 /* Receive overrun */
378 #define MACB_OVR_SIZE 1
379
380 /* Bitfields in ISR/IER/IDR/IMR */
381 #define MACB_MFD_OFFSET 0 /* Management frame sent */
382 #define MACB_MFD_SIZE 1
383 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
384 #define MACB_RCOMP_SIZE 1
385 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
386 #define MACB_RXUBR_SIZE 1
387 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
388 #define MACB_TXUBR_SIZE 1
389 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
390 #define MACB_ISR_TUND_SIZE 1
391 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
392 #define MACB_ISR_RLE_SIZE 1
393 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
394 #define MACB_TXERR_SIZE 1
395 #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */
396 #define MACB_RM9200_TBRE_SIZE 1
397 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
398 #define MACB_TCOMP_SIZE 1
399 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
400 #define MACB_ISR_LINK_SIZE 1
401 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
402 #define MACB_ISR_ROVR_SIZE 1
403 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
404 #define MACB_HRESP_SIZE 1
405 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
406 #define MACB_PFR_SIZE 1
407 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
408 #define MACB_PTZ_SIZE 1
409 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
410 #define MACB_WOL_SIZE 1
411 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
412 #define MACB_DRQFR_SIZE 1
413 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
414 #define MACB_SFR_SIZE 1
415 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
416 #define MACB_DRQFT_SIZE 1
417 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
418 #define MACB_SFT_SIZE 1
419 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
420 #define MACB_PDRQFR_SIZE 1
421 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
422 #define MACB_PDRSFR_SIZE 1
423 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
424 #define MACB_PDRQFT_SIZE 1
425 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
426 #define MACB_PDRSFT_SIZE 1
427 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
428 #define MACB_SRI_SIZE 1
429 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
430 #define GEM_WOL_SIZE 1
431
432 /* Timer increment fields */
433 #define MACB_TI_CNS_OFFSET 0
434 #define MACB_TI_CNS_SIZE 8
435 #define MACB_TI_ACNS_OFFSET 8
436 #define MACB_TI_ACNS_SIZE 8
437 #define MACB_TI_NIT_OFFSET 16
438 #define MACB_TI_NIT_SIZE 8
439
440 /* Bitfields in MAN */
441 #define MACB_DATA_OFFSET 0 /* data */
442 #define MACB_DATA_SIZE 16
443 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
444 #define MACB_CODE_SIZE 2
445 #define MACB_REGA_OFFSET 18 /* Register address */
446 #define MACB_REGA_SIZE 5
447 #define MACB_PHYA_OFFSET 23 /* PHY address */
448 #define MACB_PHYA_SIZE 5
449 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
450 #define MACB_RW_SIZE 2
451 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
452 #define MACB_SOF_SIZE 2
453
454 /* Bitfields in USRIO (AVR32) */
455 #define MACB_MII_OFFSET 0
456 #define MACB_MII_SIZE 1
457 #define MACB_EAM_OFFSET 1
458 #define MACB_EAM_SIZE 1
459 #define MACB_TX_PAUSE_OFFSET 2
460 #define MACB_TX_PAUSE_SIZE 1
461 #define MACB_TX_PAUSE_ZERO_OFFSET 3
462 #define MACB_TX_PAUSE_ZERO_SIZE 1
463
464 /* Bitfields in USRIO (AT91) */
465 #define MACB_RMII_OFFSET 0
466 #define MACB_RMII_SIZE 1
467 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
468 #define GEM_RGMII_SIZE 1
469 #define MACB_CLKEN_OFFSET 1
470 #define MACB_CLKEN_SIZE 1
471
472 /* Bitfields in WOL */
473 #define MACB_IP_OFFSET 0
474 #define MACB_IP_SIZE 16
475 #define MACB_MAG_OFFSET 16
476 #define MACB_MAG_SIZE 1
477 #define MACB_ARP_OFFSET 17
478 #define MACB_ARP_SIZE 1
479 #define MACB_SA1_OFFSET 18
480 #define MACB_SA1_SIZE 1
481 #define MACB_WOL_MTI_OFFSET 19
482 #define MACB_WOL_MTI_SIZE 1
483
484 /* Bitfields in MID */
485 #define MACB_IDNUM_OFFSET 16
486 #define MACB_IDNUM_SIZE 12
487 #define MACB_REV_OFFSET 0
488 #define MACB_REV_SIZE 16
489
490 /* Bitfield in HS_MAC_CONFIG */
491 #define GEM_HS_MAC_SPEED_OFFSET 0
492 #define GEM_HS_MAC_SPEED_SIZE 3
493
494 /* Bitfields in PCSCNTRL */
495 #define GEM_PCSAUTONEG_OFFSET 12
496 #define GEM_PCSAUTONEG_SIZE 1
497
498 /* Bitfields in DCFG1. */
499 #define GEM_IRQCOR_OFFSET 23
500 #define GEM_IRQCOR_SIZE 1
501 #define GEM_DBWDEF_OFFSET 25
502 #define GEM_DBWDEF_SIZE 3
503 #define GEM_NO_PCS_OFFSET 0
504 #define GEM_NO_PCS_SIZE 1
505
506 /* Bitfields in DCFG2. */
507 #define GEM_RX_PKT_BUFF_OFFSET 20
508 #define GEM_RX_PKT_BUFF_SIZE 1
509 #define GEM_TX_PKT_BUFF_OFFSET 21
510 #define GEM_TX_PKT_BUFF_SIZE 1
511
512
513 /* Bitfields in DCFG5. */
514 #define GEM_TSU_OFFSET 8
515 #define GEM_TSU_SIZE 1
516
517 /* Bitfields in DCFG6. */
518 #define GEM_PBUF_LSO_OFFSET 27
519 #define GEM_PBUF_LSO_SIZE 1
520 #define GEM_DAW64_OFFSET 23
521 #define GEM_DAW64_SIZE 1
522
523 /* Bitfields in DCFG8. */
524 #define GEM_T1SCR_OFFSET 24
525 #define GEM_T1SCR_SIZE 8
526 #define GEM_T2SCR_OFFSET 16
527 #define GEM_T2SCR_SIZE 8
528 #define GEM_SCR2ETH_OFFSET 8
529 #define GEM_SCR2ETH_SIZE 8
530 #define GEM_SCR2CMP_OFFSET 0
531 #define GEM_SCR2CMP_SIZE 8
532
533 /* Bitfields in DCFG10 */
534 #define GEM_TXBD_RDBUFF_OFFSET 12
535 #define GEM_TXBD_RDBUFF_SIZE 4
536 #define GEM_RXBD_RDBUFF_OFFSET 8
537 #define GEM_RXBD_RDBUFF_SIZE 4
538
539 /* Bitfields in DCFG12. */
540 #define GEM_HIGH_SPEED_OFFSET 26
541 #define GEM_HIGH_SPEED_SIZE 1
542
543 /* Bitfields in USX_CONTROL. */
544 #define GEM_USX_CTRL_SPEED_OFFSET 14
545 #define GEM_USX_CTRL_SPEED_SIZE 3
546 #define GEM_SERDES_RATE_OFFSET 12
547 #define GEM_SERDES_RATE_SIZE 2
548 #define GEM_RX_SCR_BYPASS_OFFSET 9
549 #define GEM_RX_SCR_BYPASS_SIZE 1
550 #define GEM_TX_SCR_BYPASS_OFFSET 8
551 #define GEM_TX_SCR_BYPASS_SIZE 1
552 #define GEM_TX_EN_OFFSET 1
553 #define GEM_TX_EN_SIZE 1
554 #define GEM_SIGNAL_OK_OFFSET 0
555 #define GEM_SIGNAL_OK_SIZE 1
556
557 /* Bitfields in USX_STATUS. */
558 #define GEM_USX_BLOCK_LOCK_OFFSET 0
559 #define GEM_USX_BLOCK_LOCK_SIZE 1
560
561 /* Bitfields in TISUBN */
562 #define GEM_SUBNSINCR_OFFSET 0
563 #define GEM_SUBNSINCRL_OFFSET 24
564 #define GEM_SUBNSINCRL_SIZE 8
565 #define GEM_SUBNSINCRH_OFFSET 0
566 #define GEM_SUBNSINCRH_SIZE 16
567 #define GEM_SUBNSINCR_SIZE 24
568
569 /* Bitfields in TI */
570 #define GEM_NSINCR_OFFSET 0
571 #define GEM_NSINCR_SIZE 8
572
573 /* Bitfields in TSH */
574 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
575 #define GEM_TSH_SIZE 16
576
577 /* Bitfields in TSL */
578 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
579 #define GEM_TSL_SIZE 32
580
581 /* Bitfields in TN */
582 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
583 #define GEM_TN_SIZE 30
584
585 /* Bitfields in TXBDCTRL */
586 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
587 #define GEM_TXTSMODE_SIZE 2
588
589 /* Bitfields in RXBDCTRL */
590 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
591 #define GEM_RXTSMODE_SIZE 2
592
593 /* Bitfields in SCRT2 */
594 #define GEM_QUEUE_OFFSET 0 /* Queue Number */
595 #define GEM_QUEUE_SIZE 4
596 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
597 #define GEM_VLANPR_SIZE 3
598 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
599 #define GEM_VLANEN_SIZE 1
600 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
601 #define GEM_ETHT2IDX_SIZE 3
602 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
603 #define GEM_ETHTEN_SIZE 1
604 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
605 #define GEM_CMPA_SIZE 5
606 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
607 #define GEM_CMPAEN_SIZE 1
608 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
609 #define GEM_CMPB_SIZE 5
610 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
611 #define GEM_CMPBEN_SIZE 1
612 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
613 #define GEM_CMPC_SIZE 5
614 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
615 #define GEM_CMPCEN_SIZE 1
616
617 /* Bitfields in ETHT */
618 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
619 #define GEM_ETHTCMP_SIZE 16
620
621 /* Bitfields in T2CMPW0 */
622 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
623 #define GEM_T2CMP_SIZE 16
624 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
625 #define GEM_T2MASK_SIZE 16
626
627 /* Bitfields in T2CMPW1 */
628 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
629 #define GEM_T2DISMSK_SIZE 1
630 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
631 #define GEM_T2CMPOFST_SIZE 2
632 #define GEM_T2OFST_OFFSET 0 /* offset value */
633 #define GEM_T2OFST_SIZE 7
634
635 /* Offset for screener type 2 compare values (T2CMPOFST).
636 * Note the offset is applied after the specified point,
637 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
638 * of 12 bytes from this would be the source IP address in an IP header
639 */
640 #define GEM_T2COMPOFST_SOF 0
641 #define GEM_T2COMPOFST_ETYPE 1
642 #define GEM_T2COMPOFST_IPHDR 2
643 #define GEM_T2COMPOFST_TCPUDP 3
644
645 /* offset from EtherType to IP address */
646 #define ETYPE_SRCIP_OFFSET 12
647 #define ETYPE_DSTIP_OFFSET 16
648
649 /* offset from IP header to port */
650 #define IPHDR_SRCPORT_OFFSET 0
651 #define IPHDR_DSTPORT_OFFSET 2
652
653 /* Transmit DMA buffer descriptor Word 1 */
654 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
655 #define GEM_DMA_TXVALID_SIZE 1
656
657 /* Receive DMA buffer descriptor Word 0 */
658 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
659 #define GEM_DMA_RXVALID_SIZE 1
660
661 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
662 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
663 #define GEM_DMA_SECL_SIZE 2
664 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
665 #define GEM_DMA_NSEC_SIZE 30
666
667 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
668
669 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
670 * Old hardware supports only 6 bit precision but it is enough for PTP.
671 * Less accuracy is used always instead of checking hardware version.
672 */
673 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
674 #define GEM_DMA_SECH_SIZE 4
675 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
676 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
677 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
678
679 /* Bitfields in ADJ */
680 #define GEM_ADDSUB_OFFSET 31
681 #define GEM_ADDSUB_SIZE 1
682 /* Constants for CLK */
683 #define MACB_CLK_DIV8 0
684 #define MACB_CLK_DIV16 1
685 #define MACB_CLK_DIV32 2
686 #define MACB_CLK_DIV64 3
687
688 /* GEM specific constants for CLK. */
689 #define GEM_CLK_DIV8 0
690 #define GEM_CLK_DIV16 1
691 #define GEM_CLK_DIV32 2
692 #define GEM_CLK_DIV48 3
693 #define GEM_CLK_DIV64 4
694 #define GEM_CLK_DIV96 5
695
696 /* Constants for MAN register */
697 #define MACB_MAN_C22_SOF 1
698 #define MACB_MAN_C22_WRITE 1
699 #define MACB_MAN_C22_READ 2
700 #define MACB_MAN_C22_CODE 2
701
702 #define MACB_MAN_C45_SOF 0
703 #define MACB_MAN_C45_ADDR 0
704 #define MACB_MAN_C45_WRITE 1
705 #define MACB_MAN_C45_POST_READ_INCR 2
706 #define MACB_MAN_C45_READ 3
707 #define MACB_MAN_C45_CODE 2
708
709 /* Capability mask bits */
710 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
711 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
712 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
713 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
714 #define MACB_CAPS_USRIO_DISABLED 0x00000010
715 #define MACB_CAPS_JUMBO 0x00000020
716 #define MACB_CAPS_GEM_HAS_PTP 0x00000040
717 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
718 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
719 #define MACB_CAPS_MIIONRGMII 0x00000200
720 #define MACB_CAPS_NEED_TSUCLK 0x00000400
721 #define MACB_CAPS_PCS 0x01000000
722 #define MACB_CAPS_HIGH_SPEED 0x02000000
723 #define MACB_CAPS_CLK_HW_CHG 0x04000000
724 #define MACB_CAPS_MACB_IS_EMAC 0x08000000
725 #define MACB_CAPS_FIFO_MODE 0x10000000
726 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
727 #define MACB_CAPS_SG_DISABLED 0x40000000
728 #define MACB_CAPS_MACB_IS_GEM 0x80000000
729
730 /* LSO settings */
731 #define MACB_LSO_UFO_ENABLE 0x01
732 #define MACB_LSO_TSO_ENABLE 0x02
733
734 /* Bit manipulation macros */
735 #define MACB_BIT(name) \
736 (1 << MACB_##name##_OFFSET)
737 #define MACB_BF(name,value) \
738 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
739 << MACB_##name##_OFFSET)
740 #define MACB_BFEXT(name,value)\
741 (((value) >> MACB_##name##_OFFSET) \
742 & ((1 << MACB_##name##_SIZE) - 1))
743 #define MACB_BFINS(name,value,old) \
744 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
745 << MACB_##name##_OFFSET)) \
746 | MACB_BF(name,value))
747
748 #define GEM_BIT(name) \
749 (1 << GEM_##name##_OFFSET)
750 #define GEM_BF(name, value) \
751 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
752 << GEM_##name##_OFFSET)
753 #define GEM_BFEXT(name, value)\
754 (((value) >> GEM_##name##_OFFSET) \
755 & ((1 << GEM_##name##_SIZE) - 1))
756 #define GEM_BFINS(name, value, old) \
757 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
758 << GEM_##name##_OFFSET)) \
759 | GEM_BF(name, value))
760
761 /* Register access macros */
762 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
763 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
764 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
765 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
766 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
767 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
768 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
769 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
770
771 #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
772
773 /* Conditional GEM/MACB macros. These perform the operation to the correct
774 * register dependent on whether the device is a GEM or a MACB. For registers
775 * and bitfields that are common across both devices, use macb_{read,write}l
776 * to avoid the cost of the conditional.
777 */
778 #define macb_or_gem_writel(__bp, __reg, __value) \
779 ({ \
780 if (macb_is_gem((__bp))) \
781 gem_writel((__bp), __reg, __value); \
782 else \
783 macb_writel((__bp), __reg, __value); \
784 })
785
786 #define macb_or_gem_readl(__bp, __reg) \
787 ({ \
788 u32 __v; \
789 if (macb_is_gem((__bp))) \
790 __v = gem_readl((__bp), __reg); \
791 else \
792 __v = macb_readl((__bp), __reg); \
793 __v; \
794 })
795
796 #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
797
798 /* struct macb_dma_desc - Hardware DMA descriptor
799 * @addr: DMA address of data buffer
800 * @ctrl: Control and status bits
801 */
802 struct macb_dma_desc {
803 u32 addr;
804 u32 ctrl;
805 };
806
807 #ifdef MACB_EXT_DESC
808 #define HW_DMA_CAP_32B 0
809 #define HW_DMA_CAP_64B (1 << 0)
810 #define HW_DMA_CAP_PTP (1 << 1)
811 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
812
813 struct macb_dma_desc_64 {
814 u32 addrh;
815 u32 resvd;
816 };
817
818 struct macb_dma_desc_ptp {
819 u32 ts_1;
820 u32 ts_2;
821 };
822
823 struct gem_tx_ts {
824 struct sk_buff *skb;
825 struct macb_dma_desc_ptp desc_ptp;
826 };
827 #endif
828
829 /* DMA descriptor bitfields */
830 #define MACB_RX_USED_OFFSET 0
831 #define MACB_RX_USED_SIZE 1
832 #define MACB_RX_WRAP_OFFSET 1
833 #define MACB_RX_WRAP_SIZE 1
834 #define MACB_RX_WADDR_OFFSET 2
835 #define MACB_RX_WADDR_SIZE 30
836
837 #define MACB_RX_FRMLEN_OFFSET 0
838 #define MACB_RX_FRMLEN_SIZE 12
839 #define MACB_RX_OFFSET_OFFSET 12
840 #define MACB_RX_OFFSET_SIZE 2
841 #define MACB_RX_SOF_OFFSET 14
842 #define MACB_RX_SOF_SIZE 1
843 #define MACB_RX_EOF_OFFSET 15
844 #define MACB_RX_EOF_SIZE 1
845 #define MACB_RX_CFI_OFFSET 16
846 #define MACB_RX_CFI_SIZE 1
847 #define MACB_RX_VLAN_PRI_OFFSET 17
848 #define MACB_RX_VLAN_PRI_SIZE 3
849 #define MACB_RX_PRI_TAG_OFFSET 20
850 #define MACB_RX_PRI_TAG_SIZE 1
851 #define MACB_RX_VLAN_TAG_OFFSET 21
852 #define MACB_RX_VLAN_TAG_SIZE 1
853 #define MACB_RX_TYPEID_MATCH_OFFSET 22
854 #define MACB_RX_TYPEID_MATCH_SIZE 1
855 #define MACB_RX_SA4_MATCH_OFFSET 23
856 #define MACB_RX_SA4_MATCH_SIZE 1
857 #define MACB_RX_SA3_MATCH_OFFSET 24
858 #define MACB_RX_SA3_MATCH_SIZE 1
859 #define MACB_RX_SA2_MATCH_OFFSET 25
860 #define MACB_RX_SA2_MATCH_SIZE 1
861 #define MACB_RX_SA1_MATCH_OFFSET 26
862 #define MACB_RX_SA1_MATCH_SIZE 1
863 #define MACB_RX_EXT_MATCH_OFFSET 28
864 #define MACB_RX_EXT_MATCH_SIZE 1
865 #define MACB_RX_UHASH_MATCH_OFFSET 29
866 #define MACB_RX_UHASH_MATCH_SIZE 1
867 #define MACB_RX_MHASH_MATCH_OFFSET 30
868 #define MACB_RX_MHASH_MATCH_SIZE 1
869 #define MACB_RX_BROADCAST_OFFSET 31
870 #define MACB_RX_BROADCAST_SIZE 1
871
872 #define MACB_RX_FRMLEN_MASK 0xFFF
873 #define MACB_RX_JFRMLEN_MASK 0x3FFF
874
875 /* RX checksum offload disabled: bit 24 clear in NCFGR */
876 #define GEM_RX_TYPEID_MATCH_OFFSET 22
877 #define GEM_RX_TYPEID_MATCH_SIZE 2
878
879 /* RX checksum offload enabled: bit 24 set in NCFGR */
880 #define GEM_RX_CSUM_OFFSET 22
881 #define GEM_RX_CSUM_SIZE 2
882
883 #define MACB_TX_FRMLEN_OFFSET 0
884 #define MACB_TX_FRMLEN_SIZE 11
885 #define MACB_TX_LAST_OFFSET 15
886 #define MACB_TX_LAST_SIZE 1
887 #define MACB_TX_NOCRC_OFFSET 16
888 #define MACB_TX_NOCRC_SIZE 1
889 #define MACB_MSS_MFS_OFFSET 16
890 #define MACB_MSS_MFS_SIZE 14
891 #define MACB_TX_LSO_OFFSET 17
892 #define MACB_TX_LSO_SIZE 2
893 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
894 #define MACB_TX_TCP_SEQ_SRC_SIZE 1
895 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
896 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
897 #define MACB_TX_UNDERRUN_OFFSET 28
898 #define MACB_TX_UNDERRUN_SIZE 1
899 #define MACB_TX_ERROR_OFFSET 29
900 #define MACB_TX_ERROR_SIZE 1
901 #define MACB_TX_WRAP_OFFSET 30
902 #define MACB_TX_WRAP_SIZE 1
903 #define MACB_TX_USED_OFFSET 31
904 #define MACB_TX_USED_SIZE 1
905
906 #define GEM_TX_FRMLEN_OFFSET 0
907 #define GEM_TX_FRMLEN_SIZE 14
908
909 /* Buffer descriptor constants */
910 #define GEM_RX_CSUM_NONE 0
911 #define GEM_RX_CSUM_IP_ONLY 1
912 #define GEM_RX_CSUM_IP_TCP 2
913 #define GEM_RX_CSUM_IP_UDP 3
914
915 /* limit RX checksum offload to TCP and UDP packets */
916 #define GEM_RX_CSUM_CHECKED_MASK 2
917
918 /* Scaled PPM fraction */
919 #define PPM_FRACTION 16
920
921 /* struct macb_tx_skb - data about an skb which is being transmitted
922 * @skb: skb currently being transmitted, only set for the last buffer
923 * of the frame
924 * @mapping: DMA address of the skb's fragment buffer
925 * @size: size of the DMA mapped buffer
926 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
927 * false when buffer was mapped with dma_map_single()
928 */
929 struct macb_tx_skb {
930 struct sk_buff *skb;
931 dma_addr_t mapping;
932 size_t size;
933 bool mapped_as_page;
934 };
935
936 /* Hardware-collected statistics. Used when updating the network
937 * device stats by a periodic timer.
938 */
939 struct macb_stats {
940 u32 rx_pause_frames;
941 u32 tx_ok;
942 u32 tx_single_cols;
943 u32 tx_multiple_cols;
944 u32 rx_ok;
945 u32 rx_fcs_errors;
946 u32 rx_align_errors;
947 u32 tx_deferred;
948 u32 tx_late_cols;
949 u32 tx_excessive_cols;
950 u32 tx_underruns;
951 u32 tx_carrier_errors;
952 u32 rx_resource_errors;
953 u32 rx_overruns;
954 u32 rx_symbol_errors;
955 u32 rx_oversize_pkts;
956 u32 rx_jabbers;
957 u32 rx_undersize_pkts;
958 u32 sqe_test_errors;
959 u32 rx_length_mismatch;
960 u32 tx_pause_frames;
961 };
962
963 struct gem_stats {
964 u32 tx_octets_31_0;
965 u32 tx_octets_47_32;
966 u32 tx_frames;
967 u32 tx_broadcast_frames;
968 u32 tx_multicast_frames;
969 u32 tx_pause_frames;
970 u32 tx_64_byte_frames;
971 u32 tx_65_127_byte_frames;
972 u32 tx_128_255_byte_frames;
973 u32 tx_256_511_byte_frames;
974 u32 tx_512_1023_byte_frames;
975 u32 tx_1024_1518_byte_frames;
976 u32 tx_greater_than_1518_byte_frames;
977 u32 tx_underrun;
978 u32 tx_single_collision_frames;
979 u32 tx_multiple_collision_frames;
980 u32 tx_excessive_collisions;
981 u32 tx_late_collisions;
982 u32 tx_deferred_frames;
983 u32 tx_carrier_sense_errors;
984 u32 rx_octets_31_0;
985 u32 rx_octets_47_32;
986 u32 rx_frames;
987 u32 rx_broadcast_frames;
988 u32 rx_multicast_frames;
989 u32 rx_pause_frames;
990 u32 rx_64_byte_frames;
991 u32 rx_65_127_byte_frames;
992 u32 rx_128_255_byte_frames;
993 u32 rx_256_511_byte_frames;
994 u32 rx_512_1023_byte_frames;
995 u32 rx_1024_1518_byte_frames;
996 u32 rx_greater_than_1518_byte_frames;
997 u32 rx_undersized_frames;
998 u32 rx_oversize_frames;
999 u32 rx_jabbers;
1000 u32 rx_frame_check_sequence_errors;
1001 u32 rx_length_field_frame_errors;
1002 u32 rx_symbol_errors;
1003 u32 rx_alignment_errors;
1004 u32 rx_resource_errors;
1005 u32 rx_overruns;
1006 u32 rx_ip_header_checksum_errors;
1007 u32 rx_tcp_checksum_errors;
1008 u32 rx_udp_checksum_errors;
1009 };
1010
1011 /* Describes the name and offset of an individual statistic register, as
1012 * returned by `ethtool -S`. Also describes which net_device_stats statistics
1013 * this register should contribute to.
1014 */
1015 struct gem_statistic {
1016 char stat_string[ETH_GSTRING_LEN];
1017 int offset;
1018 u32 stat_bits;
1019 };
1020
1021 /* Bitfield defs for net_device_stat statistics */
1022 #define GEM_NDS_RXERR_OFFSET 0
1023 #define GEM_NDS_RXLENERR_OFFSET 1
1024 #define GEM_NDS_RXOVERERR_OFFSET 2
1025 #define GEM_NDS_RXCRCERR_OFFSET 3
1026 #define GEM_NDS_RXFRAMEERR_OFFSET 4
1027 #define GEM_NDS_RXFIFOERR_OFFSET 5
1028 #define GEM_NDS_TXERR_OFFSET 6
1029 #define GEM_NDS_TXABORTEDERR_OFFSET 7
1030 #define GEM_NDS_TXCARRIERERR_OFFSET 8
1031 #define GEM_NDS_TXFIFOERR_OFFSET 9
1032 #define GEM_NDS_COLLISIONS_OFFSET 10
1033
1034 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
1035 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
1036 .stat_string = title, \
1037 .offset = GEM_##name, \
1038 .stat_bits = bits \
1039 }
1040
1041 /* list of gem statistic registers. The names MUST match the
1042 * corresponding GEM_* definitions.
1043 */
1044 static const struct gem_statistic gem_statistics[] = {
1045 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
1046 GEM_STAT_TITLE(TXCNT, "tx_frames"),
1047 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
1048 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
1049 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
1050 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
1051 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
1052 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
1053 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
1054 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
1055 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
1056 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
1057 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
1058 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
1059 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
1060 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1061 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
1062 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1063 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
1064 GEM_BIT(NDS_TXERR)|
1065 GEM_BIT(NDS_TXABORTEDERR)|
1066 GEM_BIT(NDS_COLLISIONS)),
1067 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
1068 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1069 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
1070 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
1071 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1072 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
1073 GEM_STAT_TITLE(RXCNT, "rx_frames"),
1074 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
1075 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
1076 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1077 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1078 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1079 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1080 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1081 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1082 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1083 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1084 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1085 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1086 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1087 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1088 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1089 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1090 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1091 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1092 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1093 GEM_BIT(NDS_RXERR)),
1094 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1095 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1096 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1097 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1098 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1099 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1100 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1101 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1102 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1103 GEM_BIT(NDS_RXERR)),
1104 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1105 GEM_BIT(NDS_RXERR)),
1106 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1107 GEM_BIT(NDS_RXERR)),
1108 };
1109
1110 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1111
1112 #define QUEUE_STAT_TITLE(title) { \
1113 .stat_string = title, \
1114 }
1115
1116 /* per queue statistics, each should be unsigned long type */
1117 struct queue_stats {
1118 union {
1119 unsigned long first;
1120 unsigned long rx_packets;
1121 };
1122 unsigned long rx_bytes;
1123 unsigned long rx_dropped;
1124 unsigned long tx_packets;
1125 unsigned long tx_bytes;
1126 unsigned long tx_dropped;
1127 };
1128
1129 static const struct gem_statistic queue_statistics[] = {
1130 QUEUE_STAT_TITLE("rx_packets"),
1131 QUEUE_STAT_TITLE("rx_bytes"),
1132 QUEUE_STAT_TITLE("rx_dropped"),
1133 QUEUE_STAT_TITLE("tx_packets"),
1134 QUEUE_STAT_TITLE("tx_bytes"),
1135 QUEUE_STAT_TITLE("tx_dropped"),
1136 };
1137
1138 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1139
1140 struct macb;
1141 struct macb_queue;
1142
1143 struct macb_or_gem_ops {
1144 int (*mog_alloc_rx_buffers)(struct macb *bp);
1145 void (*mog_free_rx_buffers)(struct macb *bp);
1146 void (*mog_init_rings)(struct macb *bp);
1147 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1148 int budget);
1149 };
1150
1151 /* MACB-PTP interface: adapt to platform needs. */
1152 struct macb_ptp_info {
1153 void (*ptp_init)(struct net_device *ndev);
1154 void (*ptp_remove)(struct net_device *ndev);
1155 s32 (*get_ptp_max_adj)(void);
1156 unsigned int (*get_tsu_rate)(struct macb *bp);
1157 int (*get_ts_info)(struct net_device *dev,
1158 struct ethtool_ts_info *info);
1159 int (*get_hwtst)(struct net_device *netdev,
1160 struct ifreq *ifr);
1161 int (*set_hwtst)(struct net_device *netdev,
1162 struct ifreq *ifr, int cmd);
1163 };
1164
1165 struct macb_pm_data {
1166 u32 scrt2;
1167 u32 usrio;
1168 };
1169
1170 struct macb_usrio_config {
1171 u32 mii;
1172 u32 rmii;
1173 u32 rgmii;
1174 u32 refclk;
1175 u32 hdfctlen;
1176 };
1177
1178 struct macb_config {
1179 u32 caps;
1180 unsigned int dma_burst_length;
1181 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1182 struct clk **hclk, struct clk **tx_clk,
1183 struct clk **rx_clk, struct clk **tsu_clk);
1184 int (*init)(struct platform_device *pdev);
1185 int jumbo_max_len;
1186 const struct macb_usrio_config *usrio;
1187 };
1188
1189 struct tsu_incr {
1190 u32 sub_ns;
1191 u32 ns;
1192 };
1193
1194 struct macb_queue {
1195 struct macb *bp;
1196 int irq;
1197
1198 unsigned int ISR;
1199 unsigned int IER;
1200 unsigned int IDR;
1201 unsigned int IMR;
1202 unsigned int TBQP;
1203 unsigned int TBQPH;
1204 unsigned int RBQS;
1205 unsigned int RBQP;
1206 unsigned int RBQPH;
1207
1208 /* Lock to protect tx_head and tx_tail */
1209 spinlock_t tx_ptr_lock;
1210 unsigned int tx_head, tx_tail;
1211 struct macb_dma_desc *tx_ring;
1212 struct macb_tx_skb *tx_skb;
1213 dma_addr_t tx_ring_dma;
1214 struct work_struct tx_error_task;
1215 bool txubr_pending;
1216 struct napi_struct napi_tx;
1217
1218 dma_addr_t rx_ring_dma;
1219 dma_addr_t rx_buffers_dma;
1220 unsigned int rx_tail;
1221 unsigned int rx_prepared_head;
1222 struct macb_dma_desc *rx_ring;
1223 struct sk_buff **rx_skbuff;
1224 void *rx_buffers;
1225 struct napi_struct napi_rx;
1226 struct queue_stats stats;
1227
1228 #ifdef CONFIG_MACB_USE_HWSTAMP
1229 struct work_struct tx_ts_task;
1230 unsigned int tx_ts_head, tx_ts_tail;
1231 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
1232 #endif
1233 };
1234
1235 struct ethtool_rx_fs_item {
1236 struct ethtool_rx_flow_spec fs;
1237 struct list_head list;
1238 };
1239
1240 struct ethtool_rx_fs_list {
1241 struct list_head list;
1242 unsigned int count;
1243 };
1244
1245 struct macb {
1246 void __iomem *regs;
1247 bool native_io;
1248
1249 /* hardware IO accessors */
1250 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1251 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1252
1253 size_t rx_buffer_size;
1254
1255 unsigned int rx_ring_size;
1256 unsigned int tx_ring_size;
1257
1258 unsigned int num_queues;
1259 unsigned int queue_mask;
1260 struct macb_queue queues[MACB_MAX_QUEUES];
1261
1262 spinlock_t lock;
1263 struct platform_device *pdev;
1264 struct clk *pclk;
1265 struct clk *hclk;
1266 struct clk *tx_clk;
1267 struct clk *rx_clk;
1268 struct clk *tsu_clk;
1269 struct net_device *dev;
1270 union {
1271 struct macb_stats macb;
1272 struct gem_stats gem;
1273 } hw_stats;
1274
1275 struct macb_or_gem_ops macbgem_ops;
1276
1277 struct mii_bus *mii_bus;
1278 struct phylink *phylink;
1279 struct phylink_config phylink_config;
1280 struct phylink_pcs phylink_usx_pcs;
1281 struct phylink_pcs phylink_sgmii_pcs;
1282
1283 u32 caps;
1284 unsigned int dma_burst_length;
1285
1286 phy_interface_t phy_interface;
1287
1288 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
1289 struct macb_tx_skb rm9200_txq[2];
1290 unsigned int max_tx_length;
1291
1292 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1293
1294 unsigned int rx_frm_len_mask;
1295 unsigned int jumbo_max_len;
1296
1297 u32 wol;
1298
1299 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1300
1301 struct phy *sgmii_phy; /* for ZynqMP SGMII mode */
1302
1303 #ifdef MACB_EXT_DESC
1304 uint8_t hw_dma_cap;
1305 #endif
1306 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1307 unsigned int tsu_rate;
1308 struct ptp_clock *ptp_clock;
1309 struct ptp_clock_info ptp_clock_info;
1310 struct tsu_incr tsu_incr;
1311 struct hwtstamp_config tstamp_config;
1312
1313 /* RX queue filer rule set*/
1314 struct ethtool_rx_fs_list rx_fs_list;
1315 spinlock_t rx_fs_lock;
1316 unsigned int max_tuples;
1317
1318 struct tasklet_struct hresp_err_tasklet;
1319
1320 int rx_bd_rd_prefetch;
1321 int tx_bd_rd_prefetch;
1322
1323 u32 rx_intr_mask;
1324
1325 struct macb_pm_data pm_data;
1326 const struct macb_usrio_config *usrio;
1327 };
1328
1329 #ifdef CONFIG_MACB_USE_HWSTAMP
1330 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1331 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1332 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1333
1334 enum macb_bd_control {
1335 TSTAMP_DISABLED,
1336 TSTAMP_FRAME_PTP_EVENT_ONLY,
1337 TSTAMP_ALL_PTP_FRAMES,
1338 TSTAMP_ALL_FRAMES,
1339 };
1340
1341 void gem_ptp_init(struct net_device *ndev);
1342 void gem_ptp_remove(struct net_device *ndev);
1343 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1344 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
gem_ptp_do_txstamp(struct macb_queue * queue,struct sk_buff * skb,struct macb_dma_desc * desc)1345 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1346 {
1347 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1348 return -ENOTSUPP;
1349
1350 return gem_ptp_txstamp(queue, skb, desc);
1351 }
1352
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1353 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1354 {
1355 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1356 return;
1357
1358 gem_ptp_rxstamp(bp, skb, desc);
1359 }
1360 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1361 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1362 #else
gem_ptp_init(struct net_device * ndev)1363 static inline void gem_ptp_init(struct net_device *ndev) { }
gem_ptp_remove(struct net_device * ndev)1364 static inline void gem_ptp_remove(struct net_device *ndev) { }
1365
gem_ptp_do_txstamp(struct macb_queue * queue,struct sk_buff * skb,struct macb_dma_desc * desc)1366 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1367 {
1368 return -1;
1369 }
1370
gem_ptp_do_rxstamp(struct macb * bp,struct sk_buff * skb,struct macb_dma_desc * desc)1371 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1372 #endif
1373
macb_is_gem(struct macb * bp)1374 static inline bool macb_is_gem(struct macb *bp)
1375 {
1376 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1377 }
1378
gem_has_ptp(struct macb * bp)1379 static inline bool gem_has_ptp(struct macb *bp)
1380 {
1381 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1382 }
1383
1384 /**
1385 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
1386 * @pclk: platform clock
1387 * @hclk: AHB clock
1388 */
1389 struct macb_platform_data {
1390 struct clk *pclk;
1391 struct clk *hclk;
1392 };
1393
1394 #endif /* _MACB_H */
1395
