Searched refs:LVDS (Results 1 – 25 of 80) sorted by relevance
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1 Device-Tree bindings for LVDS Display Bridge (ldb)3 LVDS Display Bridge6 The LVDS Display Bridge device tree node contains up to two lvds-channel7 nodes describing each of the two LVDS encoder channels of the bridge.15 interfaces as input for each LVDS channel.17 The phandle points to the iomuxc-gpr region containing the LVDS23 "di0_pll" - LDB LVDS channel 0 mux24 "di1_pll" - LDB LVDS channel 1 mux25 "di0" - LDB LVDS channel 0 gate26 "di1" - LDB LVDS channel 1 gate[all …]
85 Support for i.MX8MP DPI-to-LVDS on-SoC encoder.119 tristate "Lontium LT9211 DSI/LVDS/DPI bridge"126 Driver for Lontium LT9211 Single/Dual-Link DSI/LVDS or Single DPI127 input to Single-link/Dual-Link DSI/LVDS or Single DPI output bridge168 tristate "Transparent LVDS encoders and decoders support"173 Support for transparent LVDS encoders and decoders that don't183 GE B850v3 that convert dual channel LVDS204 tristate "NXP PTN3460 DP/LVDS bridge"209 NXP PTN3460 eDP-LVDS bridge chip driver.212 tristate "Parade eDP/LVDS bridge"[all …]
23 /* This turns the LVDS transceiver on */34 * This switches the LVDS transceiver to the single-channel45 * This switches the LVDS transceiver to the 24-bit RGB mode.57 * This switches the LVDS transceiver to VESA color mapping mode.
31 * This switches the LVDS transceiver to VESA color mapping mode.43 * This switches the LVDS transceiver to the 24-bit RGB mode.53 * This switches the LVDS transceiver to the single-channel63 /* This turns the LVDS transceiver on */
3 /* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */33 /* Texas Instruments SN75LVDS83B LVDS Transmitter */
4 tristate "Freescale i.MX8QM LVDS display bridge"9 Choose this to enable the internal LVDS Display Bridge(LDB) found in13 tristate "Freescale i.MX8QXP LVDS display bridge"18 Choose this to enable the internal LVDS Display Bridge(LDB) found in
4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel68 * When GP0_17 is low LVDS[01] are connected to the LVDS connector69 * When GP0_17 is high LVDS[01] are connected to the LT8918L
3 * Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts20 * When GP1_20 is LOW LVDS0 is connected to the LVDS connector
4 * to an Advantech IDK-1110WR 10.1" LVDS panel
4 * Advantech IDK-1110WR 10.1" LVDS panel
3 * Device Tree Source for the Advantech idk-1110wr LVDS panel connected
83 bool "Rockchip LVDS support"87 Choose this option to enable support for Rockchip LVDS controllers.88 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it89 support LVDS, rgb, dual LVDS output mode. say Y to enable its
1 TC358764 MIPI-DSI to LVDS panel bridge14 1: LVDS Output, mandatory
2 STDP4028-ge-b850v3-fw bridges (LVDS-DP)7 Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
28 tristate "Support for LVDS displays"33 Choose this to enable the internal LVDS Display Bridge (LDB)
12 tristate "Mixel LVDS PHY support"17 Enable this to add support for the Mixel LVDS PHY as found
33 bool "R-Car DU LVDS Encoder Support"37 Enable support for the R-Car Display Unit embedded LVDS encoders.
1 Rockchip RK3288 LVDS interface22 - phys: LVDS/DSI DPHY (px30 only)
227 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()247 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()248 REG_READ(LVDS); in psb_intel_crtc_mode_set()319 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in psb_intel_crtc_clock_get()
87 1 = differential (defaults to LVDS levels)123 silabs,format = <1>; /* LVDS 3v3 */131 * LVDS 1v8135 silabs,format = <1>; /* LVDS 1v8 */
