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Searched refs:L3 (Results 1 – 25 of 78) sorted by relevance

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/Linux-v6.1/net/l3mdev/
DKconfig3 # Configuration for L3 master device support
7 bool "L3 Master device support"
11 drivers to support L3 master devices like VRF.
/Linux-v6.1/Documentation/networking/
Dipvlan.rst13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
42 L3 bridge mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
64 that in L3 mode the slaves wont receive any multicast / broadcast traffic.
65 L3 mode is more restrictive since routing is controlled from the other (mostly)
76 4.2 L3 mode:
79 In this mode TX processing up to L3 happens on the stack instance attached
88 This is very similar to the L3 mode except that iptables (conn-tracking)
89 works in this mode and hence it is L3-symmetric (L3s). This will have slightly less
90 performance but that shouldn't matter since you are choosing this mode over plain-L3
Dbareudp.rst7 There are various L3 encapsulation standards using UDP being discussed to
11 The Bareudp tunnel module provides a generic L3 encapsulation support for
12 tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel.
30 This creates a bareudp tunnel device which tunnels L3 traffic with ethertype
/Linux-v6.1/Documentation/devicetree/bindings/edac/
Dapm-xgene-edac.txt8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
42 - reg : First resource shall be the L3 EDAC resource.
/Linux-v6.1/arch/arm64/boot/dts/amd/
Damd-seattle-cpus.dtsi170 next-level-cache = <&L3>;
178 next-level-cache = <&L3>;
186 next-level-cache = <&L3>;
194 next-level-cache = <&L3>;
197 L3: l3-cache { label
/Linux-v6.1/arch/powerpc/perf/
Disa207-common.c229 ret = PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
264 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
266 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in isa207_find_source()
273 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
275 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()
/Linux-v6.1/Documentation/admin-guide/perf/
Dqcom_l3_pmu.rst2 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
Darm_dsu_pmu.rst5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
7 allows counting the various events related to the L3 cache, Snoop Control Unit
/Linux-v6.1/Documentation/x86/
Dresctrl.rst36 Enable code/data prioritization in L3 cache allocations.
43 L2 and L3 CDP are controlled separately.
67 Cache resource(L3/L2) subdirectory contains the following files
178 # echo L3:0=f7 > schemata
257 This contains a set of files organized by L3 domain and by
258 RDT event. E.g. on a system with two L3 domains there will
341 On current generation systems there is one L3 cache per socket and L2
343 isn't an architectural requirement. We could have multiple separate L3
391 This can occur when aggregate L2 external bandwidth is more than L3
394 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
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/Linux-v6.1/Documentation/devicetree/bindings/sound/
Domap-dmic.txt7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
Domap-mcpdm.txt7 <L3 interconnect address, size>;
18 <0x49032000 0x7f>; /* L3 Interconnect */
/Linux-v6.1/arch/x86/events/intel/
Dds.c71 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
75 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
76 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
77 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
78 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
79 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
80 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
82 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
92 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
93 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
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/Linux-v6.1/Documentation/devicetree/bindings/arm/omap/
Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/Linux-v6.1/drivers/perf/
DKconfig108 Unit (DSU). The DSU integrates one or more cores with an L3 memory
131 bool "Qualcomm Technologies L3-cache PMU"
135 Provides support for the L3 cache performance monitor unit (PMU)
137 Adds the L3 cache PMU into the perf events subsystem for
138 monitoring L3 cache events.
147 The SoC has PMU support in its L3 cache controller (L3C) and
/Linux-v6.1/arch/alpha/kernel/
Dsetup.c1280 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1291 L3 = -1; in determine_cpu_caches()
1312 L3 = -1; in determine_cpu_caches()
1343 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1357 L3 = -1; in determine_cpu_caches()
1380 L3 = -1; in determine_cpu_caches()
1387 L3 = -1; in determine_cpu_caches()
1392 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1399 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/Linux-v6.1/arch/m68k/lib/
Ddivsi3.S117 jpl L3
120 L3: movel sp@+, d2 label
Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/Linux-v6.1/Documentation/translations/zh_CN/arm64/
Dmemory.txt88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
/Linux-v6.1/arch/riscv/lib/
Dtishift.S33 beqz a2, .L3
44 .L3: label
/Linux-v6.1/lib/
Dtest_dynamic_debug.c92 enum cat_level_names { L0 = 22, L1, L2, L3, L4, L5, L6, L7 }; enumerator
135 prdbg(L3); in do_levels()
/Linux-v6.1/Documentation/translations/zh_TW/arm64/
Dmemory.txt92 | | | | +-> [20:12] L3 索引
107 | | | +----------> [28:16] L3 索引
/Linux-v6.1/arch/arm/boot/dts/
Domap4-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
176 <0x49026000 0xff>; /* L3 Interconnect */
210 <0x4902a000 0x1000>; /* L3 data port */
246 <0x4902e000 0x7f>; /* L3 Interconnect */
308 <0x49032000 0x7f>; /* L3 Interconnect */
Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
Domap5-l4-abe.dtsi53 /* L3 to L4 ABE mapping */
110 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
176 <0x49026000 0xff>; /* L3 Interconnect */
228 <0x4902e000 0x7f>; /* L3 Interconnect */
271 <0x49032000 0x7f>; /* L3 Interconnect */
/Linux-v6.1/drivers/cpufreq/
Ds5pv210-cpufreq.c110 L0, L1, L2, L3, L4, enumerator
128 {0, L3, 200*1000},
157 [L3] = {
367 if (index >= L3) in s5pv210_target()

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