Searched refs:Instruction (Results 1 – 25 of 58) sorted by relevance
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401 Instruction 106378866 0x8026B53C E52DE004 false PUSH {lr}402 Instruction 0 0x8026B540 E24DD00C false SUB sp,sp,#0xc403 Instruction 0 0x8026B544 E3A03000 false MOV r3,#0404 Instruction 0 0x8026B548 E58D3004 false STR r3,[sp,#4]405 Instruction 0 0x8026B54C E59D3004 false LDR r3,[sp,#4]406 Instruction 0 0x8026B550 E3530004 false CMP r3,#4407 Instruction 0 0x8026B554 E2833001 false ADD r3,r3,#1408 Instruction 0 0x8026B558 E58D3004 false STR r3,[sp,#4]409 Instruction 0 0x8026B55C DAFFFFFA true BLE {pc}-0x10 ; 0x8026b54c411 Instruction 319 0x8026B54C E59D3004 false LDR r3,[sp,#4][all …]
24 Power5 - PowerPC User Instruction Set Architecture Book I v2.0227 PPC970 - PowerPC User Instruction Set Architecture Book I v2.0131 Power4+ - PowerPC User Instruction Set Architecture Book I v2.0134 Power4 - PowerPC User Instruction Set Architecture Book I v2.00
63 Instruction emulation71 Instruction Data Area (SIDA), the Interception Parameters (IP) and the74 Instruction data is copied to and from the SIDA when needed. Guest88 The Secure Instruction Data Area contains instruction storage89 data. Instruction data, i.e. data being referenced by an instruction97 Instruction emulation interceptions
109 0x8 Bad (Faulting) Instruction Word BADI180 0x380 Instruction Fetch WatchPoint FWPC182 0x381 Instruction Fetch WatchPoint FWPS184 0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1186 0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2188 0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3190 0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4200 Basic Instruction Set203 Instruction formats
59 | Instruction exception handler. For a normal exit, the62 | Unimplemented Integer Instruction stack frame with85 | Instruction exception handler. If the instruction was a "chk2"120 | Instruction exception handler isp_unimp(). If the instruction is a 64-bit123 | Integer Instruction stack frame and branches to this routine.
35 Integer Instruction" exception vector #61.108 For example, if the 68060 hardware took a "Unimplemented Integer Instruction"175 address) take the Unimplemented Integer Instruction exception. When the
115 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0206 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1286 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2318 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
42 Note: Instruction emulation may not be possible in all cases. See
40 VECTOR EV_Extension ; Extn Instruction Exception121 ; Instruction fetch or Data access, under a single Exception Vector
105 VECTOR EV_TLBMissI ; 0x108, Instruction TLB miss (0x21)111 VECTOR EV_Extension ; 0x130, Extn Instruction Excp (0x26)
76 ; Instruction Error Exception Handler
80 def Instruction(self): member in LibXED
224 inst = glb_disassembler.Instruction()
5 eBPF Instruction Set Specification, v1.027 Instruction encoding47 Instruction classes
71 Select (17)------------------------------(16) Data / Instruction
23 #error Instruction buffer size too small
49 ## ISCSI CRC 32 Implementation with crc32 and pclmulqdq Instruction
201 The flags field is synthesized and may have a value when Instruction217 Instruction Trace decoding. For calls and returns, it will display the225 Instruction Trace decoding.228 Instruction Trace decoding.
66 Decode Instruction Tracing data, replacing it with synthesized events.
332 Processor with Instruction Set for Audio Effects (Jan. 14, 1999)335 Audio Effects Processor having Decoupled Instruction352 Processor with Instruction Set for Audio Effects (Jul. 27, 1999)
327 Processor with Instruction Set for Audio Effects (Jan. 14, 1999)330 Audio Effects Processor having Decoupled Instruction347 Processor with Instruction Set for Audio Effects (Jul. 27, 1999)
32 Instruction-based #VE43 Instruction-based #GP
24 CR19 Interrupt Instruction Register
48 For Programmers, Volume II-A: The MIPS64(R) Instruction,
379 iTLB|i-tlb|Instruction-TLB |
