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Searched refs:IS_VALLEYVIEW (Results 1 – 25 of 49) sorted by relevance

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/Linux-v6.1/drivers/gpu/drm/i915/display/
Dg4x_dp.c70 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_set_clock()
464 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
649 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
659 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
1261 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1318 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_init()
1339 else if (IS_VALLEYVIEW(dev_priv)) in g4x_dp_init()
1348 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || in g4x_dp_init()
Dintel_pps.c371 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
413 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
426 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1354 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1415 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
1438 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_init()
1475 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_unlock_regs_wa()
1492 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_setup()
1531 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in assert_pps_unlocked()
Dintel_dsi_vbt.c406 else if (IS_VALLEYVIEW(dev_priv)) in mipi_exec_gpio()
891 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_init()
897 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_init()
952 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_cleanup()
956 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_cleanup()
Dintel_pipe_crc.c417 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
547 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
623 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
Dintel_vga.c18 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
Dintel_cdclk.c487 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
499 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
534 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
2270 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2279 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
2880 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
2912 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3050 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3232 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
Dintel_drrs.c72 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_drrs_set_refresh_rate_pipeconf()
Dintel_crt.c356 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_mode_valid()
569 if (IS_VALLEYVIEW(dev_priv)) in intel_crt_detect_hotplug()
1004 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_init()
Dintel_crtc.c340 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) in intel_crtc_init()
485 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_pipe_update_start()
Di9xx_plane.c803 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
837 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
868 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
Dintel_lpe_audio.c186 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
Dintel_audio.c700 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in ilk_audio_codec_disable()
755 } else if (IS_VALLEYVIEW(dev_priv) || in ilk_audio_codec_enable()
939 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_audio_hooks_init()
/Linux-v6.1/drivers/gpu/drm/i915/
Dvlv_sideband.c43 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
51 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
Dvlv_suspend.c398 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
443 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
473 if (!IS_VALLEYVIEW(i915)) in vlv_suspend_init()
Di915_driver.c183 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_setup_mchbar()
1706 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_runtime_suspend()
1755 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { in intel_runtime_resume()
Di915_irq.c191 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
1593 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
1632 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
1647 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
4413 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
4465 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_handler()
4490 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_reset()
4515 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_postinstall()
Dintel_uncore.c391 if (IS_VALLEYVIEW(uncore->i915)) in __gen6_gt_wait_for_fifo()
2126 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_uncore_fw_domains_init()
2349 } else if (IS_VALLEYVIEW(i915)) { in uncore_forcewake_init()
2399 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_uncore_init_mmio()
/Linux-v6.1/drivers/gpu/drm/i915/selftests/
Dintel_uncore.c171 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
282 !IS_VALLEYVIEW(gt->i915) && in live_forcewake_domains()
/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_rc6.c567 else if (IS_VALLEYVIEW(i915)) in intel_rc6_init()
605 else if (IS_VALLEYVIEW(i915)) in intel_rc6_enable()
770 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
Dintel_rps.c704 if (IS_VALLEYVIEW(gt->i915)) in rps_set_power()
838 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1507 else if (IS_VALLEYVIEW(i915)) in intel_rps_enable()
1605 else if (IS_VALLEYVIEW(i915)) in intel_gpu_freq()
1622 else if (IS_VALLEYVIEW(i915)) in intel_freq_opcode()
1981 else if (IS_VALLEYVIEW(i915)) in intel_rps_init()
2048 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
2069 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in read_cagf()
Dselftest_rc6.c51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
Dintel_ggtt_fencing.c576 if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) { in detect_bit_6_swizzle()
851 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) in intel_ggtt_init_fences()
Dintel_gt_pm_debugfs.c280 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
311 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_gt_pm_frequency_dump()
Dintel_gt_sysfs_pm.c255 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in intel_sysfs_rc6_init()
769 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in intel_sysfs_rps_init()
Dgen7_renderclear.c402 ((IS_IVB_GT1(i915) || IS_VALLEYVIEW(i915)) ? in emit_batch()

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