Searched refs:IRQENB_FIFO1THRES (Results 1 – 2 of 2) sorted by relevance
170 IRQENB_FIFO1THRES); in tiadc_irq_h()183 } else if (status & IRQENB_FIFO1THRES) { in tiadc_irq_h()185 tiadc_writel(adc_dev, REG_IRQCLR, IRQENB_FIFO1THRES); in tiadc_irq_h()208 tiadc_writel(adc_dev, REG_IRQSTATUS, IRQENB_FIFO1THRES); in tiadc_worker_h()209 tiadc_writel(adc_dev, REG_IRQENABLE, IRQENB_FIFO1THRES); in tiadc_worker_h()288 IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | in tiadc_buffer_preenable()320 IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | in tiadc_buffer_postenable()325 irq_enable |= IRQENB_FIFO1THRES; in tiadc_buffer_postenable()338 IRQENB_FIFO1THRES | IRQENB_FIFO1OVRRUN | in tiadc_buffer_predisable()
49 #define IRQENB_FIFO1THRES BIT(5) macro
