Searched refs:IMX8ULP_CLK_FROSC_DIV2 (Results 1 – 3 of 3) sorted by relevance
227 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;240 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;273 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;288 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;316 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;329 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
41 #define IMX8ULP_CLK_FROSC_DIV2 34 macro
217 …clks[IMX8ULP_CLK_FROSC_DIV2] = imx_clk_hw_divider("frosc_div2", "frosc_div2_gate", base + 0x208, 8… in imx8ulp_clk_cgc1_init()
