Searched refs:I915_MAX_PIPES (Results 1 – 17 of 17) sorted by relevance
| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_bw.h | 26 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
44 int min_cdclk[I915_MAX_PIPES];
45 unsigned int data_rate[I915_MAX_PIPES];
46 u8 num_active_planes[I915_MAX_PIPES];
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| D | skl_watermark.h | 57 struct skl_ddb_entry ddb[I915_MAX_PIPES];
58 unsigned int weight[I915_MAX_PIPES];
59 u8 slices[I915_MAX_PIPES];
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| D | intel_cdclk.h | 42 int min_cdclk[I915_MAX_PIPES];
44 u8 min_voltage_level[I915_MAX_PIPES];
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| D | intel_frontbuffer.c | 312 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
314 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); in intel_frontbuffer_track()
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| D | intel_display_core.h | 98 struct intel_encoder *encoder_map[I915_MAX_PIPES];
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| D | intel_display.h | 96 I915_MAX_PIPES = _PIPE_EDP enumerator
377 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
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| D | intel_dvo.c | 429 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init()
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| D | intel_display_types.h | 1671 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
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| D | skl_watermark.c | 800 u8 dbuf_mask[I915_MAX_PIPES];
2951 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_dbuf_is_misconfigured()
2972 I915_MAX_PIPES, crtc->pipe)) in skl_dbuf_is_misconfigured()
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| D | intel_display.c | 7253 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()
7290 entries, I915_MAX_PIPES, pipe)) in skl_commit_modeset_enables()
7358 entries, I915_MAX_PIPES, pipe)); in skl_commit_modeset_enables()
7489 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()
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| /Linux-v6.1/drivers/gpu/drm/i915/ |
| D | intel_device_info.h | 246 u8 num_sprites[I915_MAX_PIPES];
247 u8 num_scalers[I915_MAX_PIPES];
288 u32 cursor_offsets[I915_MAX_PIPES];
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| D | i915_drv.h | 263 u32 de_irq_mask[I915_MAX_PIPES];
265 u32 pipestat_irq_mask[I915_MAX_PIPES];
328 u32 chv_dpll_md[I915_MAX_PIPES];
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| D | i915_irq.c | 1431 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument
1497 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument
1514 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument
1538 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument
1565 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument
1665 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()
1752 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()
4057 u32 pipe_stats[I915_MAX_PIPES] = {}; in i8xx_irq_handler()
4160 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()
4306 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
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| /Linux-v6.1/drivers/gpu/drm/i915/gvt/ |
| D | fb_decoder.c | 187 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()
211 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()
342 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()
421 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_sprite_plane()
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| D | fb_decoder.h | 163 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
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| D | gvt.h | 114 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
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| D | display.c | 76 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
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