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Searched refs:HHI_VIID_CLK_CNTL (Results 1 – 9 of 9) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/meson/
Dmeson_vclk.c60 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
293 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); in meson_venci_cvbs_clock_config()
304 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
307 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
311 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); in meson_venci_cvbs_clock_config()
325 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
329 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
331 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
/Linux-v6.1/drivers/clk/meson/
Daxg.h52 #define HHI_VIID_CLK_CNTL 0x12c macro
Dmeson8b.h28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
Dgxbb.h34 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ macro
Daxg.c1314 .offset = HHI_VIID_CLK_CNTL,
1405 .offset = HHI_VIID_CLK_CNTL,
1489 .offset = HHI_VIID_CLK_CNTL,
1503 .offset = HHI_VIID_CLK_CNTL,
1517 .offset = HHI_VIID_CLK_CNTL,
1531 .offset = HHI_VIID_CLK_CNTL,
1545 .offset = HHI_VIID_CLK_CNTL,
Dg12a.h55 #define HHI_VIID_CLK_CNTL 0x12C macro
Dgxbb.c1886 .offset = HHI_VIID_CLK_CNTL,
1982 .offset = HHI_VIID_CLK_CNTL,
2066 .offset = HHI_VIID_CLK_CNTL,
2080 .offset = HHI_VIID_CLK_CNTL,
2094 .offset = HHI_VIID_CLK_CNTL,
2108 .offset = HHI_VIID_CLK_CNTL,
2122 .offset = HHI_VIID_CLK_CNTL,
Dg12a.c3157 .offset = HHI_VIID_CLK_CNTL,
3248 .offset = HHI_VIID_CLK_CNTL,
3332 .offset = HHI_VIID_CLK_CNTL,
3346 .offset = HHI_VIID_CLK_CNTL,
3360 .offset = HHI_VIID_CLK_CNTL,
3374 .offset = HHI_VIID_CLK_CNTL,
3388 .offset = HHI_VIID_CLK_CNTL,
Dmeson8b.c1420 .offset = HHI_VIID_CLK_CNTL,