Searched refs:GIC (Results 1 – 25 of 59) sorted by relevance
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| /Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,gicp.txt | 4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
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| D | ti,omap4-wugen-mpu | 4 routes interrupts to the GIC, and also serves as a wakeup source. It
18 - Because this HW ultimately routes interrupts to the GIC, the
19 interrupt specifier must be that of the GIC.
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| D | mediatek,cirq.txt | 4 work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
6 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
18 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
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| D | nvidia,tegra20-ictlr.txt | 4 interrupts to the GIC, and also serves as a wakeup source. It is also
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
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| D | marvell,icu.txt | 6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
39 - msi-parent: Should point to the GICP controller, the GIC extension
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| D | marvell,armada-8k-pic.txt | 6 typically connected to the GIC as the primary interrupt controller.
15 typically the GIC
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| D | marvell,odmi-controller.txt | 23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
27 for details about the GIC Device Tree binding.
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| D | marvell,armada-370-xp-mpic.txt | 24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
25 indicate to which GIC interrupt the MPIC output is connected.
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| D | mediatek,sysirq.txt | 3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
29 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
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| D | fsl,ls-scfg-msi.txt | 17 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
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| D | amlogic,meson-gpio-intc.txt | 5 a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
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| D | hisilicon,mbigen-v2.txt | 8 To reduce the wired interrupt number connected to GIC,
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| /Linux-v6.1/arch/mips/boot/dts/mti/ |
| D | sead3.dts | 64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
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| /Linux-v6.1/drivers/net/ethernet/renesas/ |
| D | ravb_ptp.c | 202 ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); in ravb_ptp_extts()
258 ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); in ravb_ptp_perout()
270 ravb_modify(ndev, GIC, GIC_PTME, 0); in ravb_ptp_perout()
311 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt()
354 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
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| /Linux-v6.1/Documentation/virt/kvm/devices/ |
| D | arm-vgic.rst | 27 Base address in the guest physical address space of the GIC distributor
32 Base address in the guest physical address space of the GIC virtual cpu
110 a GIC without the security extensions expose group 0 and group 1 active
132 this GIC instance, ranging from 64 to 1024, in increments of 32.
138 -EBUSY Value has already be set, or GIC has already been initialized
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| D | vcpu.rst | 51 -ENODEV PMUv3 not supported or GIC not initialized
58 virtual GIC implementation, this must be done after initializing the in-kernel
70 -ENODEV PMUv3 not supported or GIC not initialized
120 -ENODEV PMUv3 not supported or GIC not initialized
159 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,vf610-mscm-ir.txt | 19 Flags get passed only when using GIC as parent. Flags
20 encoding as documented by the GIC bindings.
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | arm-realview-eb.dts | 34 * This is the core tile with the CPU and GIC etc for the
64 * to the GIC on the core tile.
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| D | arm-realview-eb-mp.dtsi | 119 * to the GIC on the core tile.
181 * GIC.
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| D | arm-realview-pb1176.dts | 332 /* Primary DevChip GIC synthesized with the CPU */
561 /* This GIC on the board is cascaded off the DevChip GIC */
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| /Linux-v6.1/Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.txt | 38 For GICv3 and GIC ITS bindings, see:
127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
134 associated with the listed GIC ITS, with the msi-specifier
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
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| /Linux-v6.1/arch/arm64/boot/dts/apm/ |
| D | apm-shadowcat.dtsi | 118 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
121 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
122 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
123 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
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| /Linux-v6.1/Documentation/devicetree/bindings/arm/ |
| D | xen.txt | 20 A GIC node is also required.
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| /Linux-v6.1/arch/arm64/boot/dts/cavium/ |
| D | thunder2-99xx.dtsi | 73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
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