Searched refs:EXYNOS_I2S_BUS (Results 1 – 10 of 10) sorted by relevance
19 #define EXYNOS_I2S_BUS 6 macro
217 clocks = <&clock_audss EXYNOS_I2S_BUS>,218 <&clock_audss EXYNOS_I2S_BUS>,
547 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
596 clocks = <&clock_audss EXYNOS_I2S_BUS>,597 <&clock_audss EXYNOS_I2S_BUS>,
528 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
494 clocks = <&clock_audss EXYNOS_I2S_BUS>,495 <&clock_audss EXYNOS_I2S_BUS>,
714 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
695 assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
80 clocks = <&clock_audss EXYNOS_I2S_BUS>,
216 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
