Searched refs:EXYNOS5_DREXI_TIMINGROW0 (Results 1 – 1 of 1) sorted by relevance
30 #define EXYNOS5_DREXI_TIMINGROW0 (0x0034) macro430 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()432 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()
