Searched refs:ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (Results 1 – 15 of 15) sorted by relevance
919 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_pcie_gart_enable()996 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_agp_enable()
645 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
107 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1283 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable()1362 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
374 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
492 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1153 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
590 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1143 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_pcie_gart_enable()1235 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_agp_enable()
2413 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_pcie_gart_enable()2496 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_agp_enable()
4302 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable()4388 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
5441 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable()5558 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
375 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
