1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _USR_IDXD_H_ 4 #define _USR_IDXD_H_ 5 6 #ifdef __KERNEL__ 7 #include <linux/types.h> 8 #else 9 #include <stdint.h> 10 #endif 11 12 /* Driver command error status */ 13 enum idxd_scmd_stat { 14 IDXD_SCMD_DEV_ENABLED = 0x80000010, 15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 16 IDXD_SCMD_WQ_ENABLED = 0x80000021, 17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 18 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 19 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 20 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 24 IDXD_SCMD_PERCPU_ERR = 0x80090000, 25 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 26 IDXD_SCMD_CDEV_ERR = 0x800b0000, 27 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 28 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 29 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 30 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 31 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 32 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, 33 }; 34 35 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 36 #define IDXD_SCMD_SOFTERR_SHIFT 16 37 38 /* Descriptor flags */ 39 #define IDXD_OP_FLAG_FENCE 0x0001 40 #define IDXD_OP_FLAG_BOF 0x0002 41 #define IDXD_OP_FLAG_CRAV 0x0004 42 #define IDXD_OP_FLAG_RCR 0x0008 43 #define IDXD_OP_FLAG_RCI 0x0010 44 #define IDXD_OP_FLAG_CRSTS 0x0020 45 #define IDXD_OP_FLAG_CR 0x0080 46 #define IDXD_OP_FLAG_CC 0x0100 47 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 48 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 49 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 50 #define IDXD_OP_FLAG_CR_TCS 0x1000 51 #define IDXD_OP_FLAG_STORD 0x2000 52 #define IDXD_OP_FLAG_DRDBK 0x4000 53 #define IDXD_OP_FLAG_DSTS 0x8000 54 55 /* IAX */ 56 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 57 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 58 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 59 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 60 #define IDXD_OP_FLAG_SRC2_STS 0x100000 61 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 62 63 /* Opcode */ 64 enum dsa_opcode { 65 DSA_OPCODE_NOOP = 0, 66 DSA_OPCODE_BATCH, 67 DSA_OPCODE_DRAIN, 68 DSA_OPCODE_MEMMOVE, 69 DSA_OPCODE_MEMFILL, 70 DSA_OPCODE_COMPARE, 71 DSA_OPCODE_COMPVAL, 72 DSA_OPCODE_CR_DELTA, 73 DSA_OPCODE_AP_DELTA, 74 DSA_OPCODE_DUALCAST, 75 DSA_OPCODE_CRCGEN = 0x10, 76 DSA_OPCODE_COPY_CRC, 77 DSA_OPCODE_DIF_CHECK, 78 DSA_OPCODE_DIF_INS, 79 DSA_OPCODE_DIF_STRP, 80 DSA_OPCODE_DIF_UPDT, 81 DSA_OPCODE_CFLUSH = 0x20, 82 }; 83 84 enum iax_opcode { 85 IAX_OPCODE_NOOP = 0, 86 IAX_OPCODE_DRAIN = 2, 87 IAX_OPCODE_MEMMOVE, 88 IAX_OPCODE_DECOMPRESS = 0x42, 89 IAX_OPCODE_COMPRESS, 90 IAX_OPCODE_CRC64, 91 IAX_OPCODE_ZERO_DECOMP_32 = 0x48, 92 IAX_OPCODE_ZERO_DECOMP_16, 93 IAX_OPCODE_ZERO_COMP_32 = 0x4c, 94 IAX_OPCODE_ZERO_COMP_16, 95 IAX_OPCODE_SCAN = 0x50, 96 IAX_OPCODE_SET_MEMBER, 97 IAX_OPCODE_EXTRACT, 98 IAX_OPCODE_SELECT, 99 IAX_OPCODE_RLE_BURST, 100 IAX_OPCODE_FIND_UNIQUE, 101 IAX_OPCODE_EXPAND, 102 }; 103 104 /* Completion record status */ 105 enum dsa_completion_status { 106 DSA_COMP_NONE = 0, 107 DSA_COMP_SUCCESS, 108 DSA_COMP_SUCCESS_PRED, 109 DSA_COMP_PAGE_FAULT_NOBOF, 110 DSA_COMP_PAGE_FAULT_IR, 111 DSA_COMP_BATCH_FAIL, 112 DSA_COMP_BATCH_PAGE_FAULT, 113 DSA_COMP_DR_OFFSET_NOINC, 114 DSA_COMP_DR_OFFSET_ERANGE, 115 DSA_COMP_DIF_ERR, 116 DSA_COMP_BAD_OPCODE = 0x10, 117 DSA_COMP_INVALID_FLAGS, 118 DSA_COMP_NOZERO_RESERVE, 119 DSA_COMP_XFER_ERANGE, 120 DSA_COMP_DESC_CNT_ERANGE, 121 DSA_COMP_DR_ERANGE, 122 DSA_COMP_OVERLAP_BUFFERS, 123 DSA_COMP_DCAST_ERR, 124 DSA_COMP_DESCLIST_ALIGN, 125 DSA_COMP_INT_HANDLE_INVAL, 126 DSA_COMP_CRA_XLAT, 127 DSA_COMP_CRA_ALIGN, 128 DSA_COMP_ADDR_ALIGN, 129 DSA_COMP_PRIV_BAD, 130 DSA_COMP_TRAFFIC_CLASS_CONF, 131 DSA_COMP_PFAULT_RDBA, 132 DSA_COMP_HW_ERR1, 133 DSA_COMP_HW_ERR_DRB, 134 DSA_COMP_TRANSLATION_FAIL, 135 }; 136 137 enum iax_completion_status { 138 IAX_COMP_NONE = 0, 139 IAX_COMP_SUCCESS, 140 IAX_COMP_PAGE_FAULT_IR = 0x04, 141 IAX_COMP_ANALYTICS_ERROR = 0x0a, 142 IAX_COMP_OUTBUF_OVERFLOW, 143 IAX_COMP_BAD_OPCODE = 0x10, 144 IAX_COMP_INVALID_FLAGS, 145 IAX_COMP_NOZERO_RESERVE, 146 IAX_COMP_INVALID_SIZE, 147 IAX_COMP_OVERLAP_BUFFERS = 0x16, 148 IAX_COMP_INT_HANDLE_INVAL = 0x19, 149 IAX_COMP_CRA_XLAT, 150 IAX_COMP_CRA_ALIGN, 151 IAX_COMP_ADDR_ALIGN, 152 IAX_COMP_PRIV_BAD, 153 IAX_COMP_TRAFFIC_CLASS_CONF, 154 IAX_COMP_PFAULT_RDBA, 155 IAX_COMP_HW_ERR1, 156 IAX_COMP_HW_ERR_DRB, 157 IAX_COMP_TRANSLATION_FAIL, 158 IAX_COMP_PRS_TIMEOUT, 159 IAX_COMP_WATCHDOG, 160 IAX_COMP_INVALID_COMP_FLAG = 0x30, 161 IAX_COMP_INVALID_FILTER_FLAG, 162 IAX_COMP_INVALID_INPUT_SIZE, 163 IAX_COMP_INVALID_NUM_ELEMS, 164 IAX_COMP_INVALID_SRC1_WIDTH, 165 IAX_COMP_INVALID_INVERT_OUT, 166 }; 167 168 #define DSA_COMP_STATUS_MASK 0x7f 169 #define DSA_COMP_STATUS_WRITE 0x80 170 171 struct dsa_hw_desc { 172 uint32_t pasid:20; 173 uint32_t rsvd:11; 174 uint32_t priv:1; 175 uint32_t flags:24; 176 uint32_t opcode:8; 177 uint64_t completion_addr; 178 union { 179 uint64_t src_addr; 180 uint64_t rdback_addr; 181 uint64_t pattern; 182 uint64_t desc_list_addr; 183 }; 184 union { 185 uint64_t dst_addr; 186 uint64_t rdback_addr2; 187 uint64_t src2_addr; 188 uint64_t comp_pattern; 189 }; 190 union { 191 uint32_t xfer_size; 192 uint32_t desc_count; 193 }; 194 uint16_t int_handle; 195 uint16_t rsvd1; 196 union { 197 uint8_t expected_res; 198 /* create delta record */ 199 struct { 200 uint64_t delta_addr; 201 uint32_t max_delta_size; 202 uint32_t delt_rsvd; 203 uint8_t expected_res_mask; 204 }; 205 uint32_t delta_rec_size; 206 uint64_t dest2; 207 /* CRC */ 208 struct { 209 uint32_t crc_seed; 210 uint32_t crc_rsvd; 211 uint64_t seed_addr; 212 }; 213 /* DIF check or strip */ 214 struct { 215 uint8_t src_dif_flags; 216 uint8_t dif_chk_res; 217 uint8_t dif_chk_flags; 218 uint8_t dif_chk_res2[5]; 219 uint32_t chk_ref_tag_seed; 220 uint16_t chk_app_tag_mask; 221 uint16_t chk_app_tag_seed; 222 }; 223 /* DIF insert */ 224 struct { 225 uint8_t dif_ins_res; 226 uint8_t dest_dif_flag; 227 uint8_t dif_ins_flags; 228 uint8_t dif_ins_res2[13]; 229 uint32_t ins_ref_tag_seed; 230 uint16_t ins_app_tag_mask; 231 uint16_t ins_app_tag_seed; 232 }; 233 /* DIF update */ 234 struct { 235 uint8_t src_upd_flags; 236 uint8_t upd_dest_flags; 237 uint8_t dif_upd_flags; 238 uint8_t dif_upd_res[5]; 239 uint32_t src_ref_tag_seed; 240 uint16_t src_app_tag_mask; 241 uint16_t src_app_tag_seed; 242 uint32_t dest_ref_tag_seed; 243 uint16_t dest_app_tag_mask; 244 uint16_t dest_app_tag_seed; 245 }; 246 247 uint8_t op_specific[24]; 248 }; 249 } __attribute__((packed)); 250 251 struct iax_hw_desc { 252 uint32_t pasid:20; 253 uint32_t rsvd:11; 254 uint32_t priv:1; 255 uint32_t flags:24; 256 uint32_t opcode:8; 257 uint64_t completion_addr; 258 uint64_t src1_addr; 259 uint64_t dst_addr; 260 uint32_t src1_size; 261 uint16_t int_handle; 262 union { 263 uint16_t compr_flags; 264 uint16_t decompr_flags; 265 }; 266 uint64_t src2_addr; 267 uint32_t max_dst_size; 268 uint32_t src2_size; 269 uint32_t filter_flags; 270 uint32_t num_inputs; 271 } __attribute__((packed)); 272 273 struct dsa_raw_desc { 274 uint64_t field[8]; 275 } __attribute__((packed)); 276 277 /* 278 * The status field will be modified by hardware, therefore it should be 279 * volatile and prevent the compiler from optimize the read. 280 */ 281 struct dsa_completion_record { 282 volatile uint8_t status; 283 union { 284 uint8_t result; 285 uint8_t dif_status; 286 }; 287 uint16_t rsvd; 288 uint32_t bytes_completed; 289 uint64_t fault_addr; 290 union { 291 /* common record */ 292 struct { 293 uint32_t invalid_flags:24; 294 uint32_t rsvd2:8; 295 }; 296 297 uint32_t delta_rec_size; 298 uint32_t crc_val; 299 300 /* DIF check & strip */ 301 struct { 302 uint32_t dif_chk_ref_tag; 303 uint16_t dif_chk_app_tag_mask; 304 uint16_t dif_chk_app_tag; 305 }; 306 307 /* DIF insert */ 308 struct { 309 uint64_t dif_ins_res; 310 uint32_t dif_ins_ref_tag; 311 uint16_t dif_ins_app_tag_mask; 312 uint16_t dif_ins_app_tag; 313 }; 314 315 /* DIF update */ 316 struct { 317 uint32_t dif_upd_src_ref_tag; 318 uint16_t dif_upd_src_app_tag_mask; 319 uint16_t dif_upd_src_app_tag; 320 uint32_t dif_upd_dest_ref_tag; 321 uint16_t dif_upd_dest_app_tag_mask; 322 uint16_t dif_upd_dest_app_tag; 323 }; 324 325 uint8_t op_specific[16]; 326 }; 327 } __attribute__((packed)); 328 329 struct dsa_raw_completion_record { 330 uint64_t field[4]; 331 } __attribute__((packed)); 332 333 struct iax_completion_record { 334 volatile uint8_t status; 335 uint8_t error_code; 336 uint16_t rsvd; 337 uint32_t bytes_completed; 338 uint64_t fault_addr; 339 uint32_t invalid_flags; 340 uint32_t rsvd2; 341 uint32_t output_size; 342 uint8_t output_bits; 343 uint8_t rsvd3; 344 uint16_t xor_csum; 345 uint32_t crc; 346 uint32_t min; 347 uint32_t max; 348 uint32_t sum; 349 uint64_t rsvd4[2]; 350 } __attribute__((packed)); 351 352 struct iax_raw_completion_record { 353 uint64_t field[8]; 354 } __attribute__((packed)); 355 356 #endif 357
