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Searched refs:DPU_REG_READ (Results 1 – 11 of 11) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_vbif.c44 pnd = DPU_REG_READ(c, VBIF_XIN_PND_ERR); in dpu_hw_clear_errors()
45 src = DPU_REG_READ(c, VBIF_XIN_SRC_ERR); in dpu_hw_clear_errors()
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
122 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_get_limit_conf()
134 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0); in dpu_hw_set_halt_ctrl()
150 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1); in dpu_hw_get_halt_ctrl()
170 reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high); in dpu_hw_set_qos_remap()
171 reg_val_lvl = DPU_REG_READ(c, reg_lvl + reg_high); in dpu_hw_set_qos_remap()
195 reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN); in dpu_hw_set_write_gather_en()
Ddpu_hw_pingpong.c141 u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG); in dpu_hw_pp_get_autorefresh_config()
187 cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC); in dpu_hw_pp_connect_external_te()
209 val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL); in dpu_hw_pp_get_vsync_info()
212 val = DPU_REG_READ(c, PP_INT_COUNT_VAL); in dpu_hw_pp_get_vsync_info()
216 val = DPU_REG_READ(c, PP_LINE_COUNT); in dpu_hw_pp_get_vsync_info()
232 init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF; in dpu_hw_pp_get_line_count()
233 height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF; in dpu_hw_pp_get_line_count()
238 line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF; in dpu_hw_pp_get_line_count()
268 data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP); in dpu_hw_pp_setup_dsc()
Ddpu_hw_intf.c114 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()
264 fetch_enable = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_prg_fetch()
284 mux_cfg = DPU_REG_READ(c, INTF_MUX); in dpu_hw_intf_bind_pingpong_blk()
301 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); in dpu_hw_intf_get_status()
302 s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); in dpu_hw_intf_get_status()
304 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT); in dpu_hw_intf_get_status()
305 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT); in dpu_hw_intf_get_status()
321 return DPU_REG_READ(c, INTF_LINE_COUNT); in dpu_hw_intf_get_line_count()
Ddpu_hw_ctl.c89 return DPU_REG_READ(c, CTL_FLUSH); in dpu_hw_ctl_get_flush_register()
101 return !!(DPU_REG_READ(&ctx->hw, CTL_START) & BIT(0)); in dpu_hw_ctl_is_started()
323 status = DPU_REG_READ(c, CTL_SW_RESET); in dpu_hw_ctl_poll_reset_status()
349 status = DPU_REG_READ(c, CTL_SW_RESET); in dpu_hw_ctl_wait_reset_status()
536 intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); in dpu_hw_ctl_intf_cfg_v1()
537 wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); in dpu_hw_ctl_intf_cfg_v1()
608 merge3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE); in dpu_hw_ctl_reset_intf_cfg_v1()
617 intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); in dpu_hw_ctl_reset_intf_cfg_v1()
623 wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); in dpu_hw_ctl_reset_intf_cfg_v1()
Ddpu_hw_top.c110 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_setup_clk_force_ctrl()
136 value = DPU_REG_READ(c, DANGER_STATUS); in dpu_hw_get_danger_status()
165 reg = DPU_REG_READ(c, MDP_VSYNC_SEL); in dpu_hw_setup_vsync_source()
212 reg = DPU_REG_READ(c, wd_ctl2); in dpu_hw_setup_vsync_source()
233 value = DPU_REG_READ(c, SAFE_STATUS); in dpu_hw_get_safe_status()
Ddpu_hw_sspp.c189 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); in dpu_hw_sspp_setup_multirect()
211 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); in _sspp_setup_opmode()
230 opmode = DPU_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); in _sspp_setup_csc10_opmode()
267 opmode = DPU_REG_READ(c, op_mode_off + idx); in dpu_hw_sspp_setup_format()
487 ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); in dpu_hw_sspp_setup_rects()
488 ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); in dpu_hw_sspp_setup_rects()
Ddpu_hw_lm.c73 op_mode = DPU_REG_READ(c, LM_OP_MODE); in dpu_hw_lm_setup_out()
156 op_mode = DPU_REG_READ(c, LM_OP_MODE); in dpu_hw_lm_setup_color3()
Ddpu_hw_interrupts.c187 irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off); in dpu_core_irq()
190 enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off); in dpu_core_irq()
386 intr_status = DPU_REG_READ(&intr->hw, in dpu_core_irq_read()
Ddpu_hw_util.c374 return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset); in dpu_hw_get_scaler3_ver()
485 ctrl = DPU_REG_READ(c, misr_ctrl_offset); in dpu_hw_collect_misr()
493 *misr_value = DPU_REG_READ(c, misr_signature_offset); in dpu_hw_collect_misr()
Ddpu_hw_util.h333 #define DPU_REG_READ(c, off) dpu_reg_read(c, off) macro
Ddpu_hw_wb.c214 mux_cfg = DPU_REG_READ(c, WB_MUX); in dpu_hw_wb_bind_pingpong_blk()