| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
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| D | sddr2.c | 63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
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| D | sddr3.c | 72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
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| /Linux-v6.1/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
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| D | sram242x.S | 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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| D | sram243x.S | 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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| /Linux-v6.1/arch/x86/boot/ |
| D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
109 dll = inb(port + DLL); in probe_baud()
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| /Linux-v6.1/tools/testing/kunit/ |
| D | .gitignore | 2 # Byte-compiled / optimized / DLL files
|
| /Linux-v6.1/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-sprd.txt | 26 PHY DLL delays are used to delay the data valid window, and align the window
27 to sampling clock. PHY DLL delays can be configured by following properties,
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| D | sdhci-st.txt | 27 to configure DLL inside the flashSS, if so reg-names must also be
32 for eMMC on stih407 family silicon to configure DLL inside FlashSS.
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| /Linux-v6.1/arch/arm/mach-orion5x/ |
| D | tsx09-common.c | 33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
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| D | terastation_pro2-setup.c | 276 writel(divisor & 0xff, UART1_REG(DLL)); in tsp2_power_off()
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| D | kurobox_pro-setup.c | 298 writel(divisor & 0xff, UART1_REG(DLL)); in kurobox_pro_power_off()
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| /Linux-v6.1/arch/x86/kernel/ |
| D | early_printk.c | 94 #define DLL 0 /* Divisor Latch Low */ macro
141 serial_out(early_serial_base, DLL, divisor & 0xff); in early_serial_hw_init()
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| /Linux-v6.1/drivers/usb/serial/ |
| D | io_16654.h | 40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB macro
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| D | io_edgeport.c | 2218 MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, DLL, LOW8(divisor)); in send_cmd_write_baud_rate()
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| /Linux-v6.1/Documentation/misc-devices/ |
| D | oxsemi-tornado.rst | 94 and the clock divisor (DLM/DLL) as follows to obtain such rates if so
101 |0 0 0| CPR2:CPR | TCR | DLM:DLL |
112 For example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL
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| /Linux-v6.1/drivers/power/reset/ |
| D | qnap-poweroff.c | 61 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_power_off()
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| /Linux-v6.1/Documentation/virt/kvm/x86/ |
| D | errata.rst | 32 Note however that any software (e.g ``WIN87EM.DLL``) expecting these features
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| /Linux-v6.1/drivers/net/hamradio/ |
| D | baycom_ser_fdx.c | 102 #define DLL(iobase) (iobase+0) macro
174 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
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| D | baycom_ser_hdx.c | 88 #define DLL(iobase) (iobase+0) macro
159 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
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| D | yam.c | 159 #define DLL(iobase) (iobase+0) macro
295 outb(1, DLL(iobase)); in fpga_reset()
467 outb(divisor, DLL(dev->base_addr)); in yam_set_uart()
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