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Searched refs:DEF_MOD (Results 1 – 25 of 27) sorted by relevance

12

/Linux-v6.1/drivers/clk/renesas/
Dr8a7742-cpg-mssr.c83 DEF_MOD("msiof0", 0, R8A7742_CLK_MP),
84 DEF_MOD("vcp1", 100, R8A7742_CLK_ZS),
85 DEF_MOD("vcp0", 101, R8A7742_CLK_ZS),
86 DEF_MOD("vpc1", 102, R8A7742_CLK_ZS),
87 DEF_MOD("vpc0", 103, R8A7742_CLK_ZS),
88 DEF_MOD("tmu1", 111, R8A7742_CLK_P),
89 DEF_MOD("3dg", 112, R8A7742_CLK_ZG),
90 DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS),
91 DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS),
92 DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS),
[all …]
Dr8a7796-cpg-mssr.c133 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
134 DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
135 DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
136 DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2),
137 DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2),
138 DEF_MOD("tmu0", 125, R8A7796_CLK_CP),
139 DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
140 DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
141 DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
142 DEF_MOD("scif1", 206, R8A7796_CLK_S3D4),
[all …]
Dr8a77965-cpg-mssr.c128 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
129 DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
130 DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
131 DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2),
132 DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2),
133 DEF_MOD("tmu0", 125, R8A77965_CLK_CP),
134 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
135 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
136 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
137 DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
[all …]
Dr8a7743-cpg-mssr.c81 DEF_MOD("msiof0", 0, R8A7743_CLK_MP),
82 DEF_MOD("vcp0", 101, R8A7743_CLK_ZS),
83 DEF_MOD("vpc0", 103, R8A7743_CLK_ZS),
84 DEF_MOD("tmu1", 111, R8A7743_CLK_P),
85 DEF_MOD("3dg", 112, R8A7743_CLK_ZG),
86 DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
87 DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
88 DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
89 DEF_MOD("tmu3", 121, R8A7743_CLK_P),
90 DEF_MOD("tmu2", 122, R8A7743_CLK_P),
[all …]
Dr8a7791-cpg-mssr.c89 DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
90 DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
91 DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
92 DEF_MOD("jpu", 106, R8A7791_CLK_M2),
93 DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
94 DEF_MOD("tmu1", 111, R8A7791_CLK_P),
95 DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
96 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
97 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
98 DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
[all …]
Dr8a7790-cpg-mssr.c92 DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
93 DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
94 DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
95 DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
96 DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
97 DEF_MOD("jpu", 106, R8A7790_CLK_M2),
98 DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
99 DEF_MOD("tmu1", 111, R8A7790_CLK_P),
100 DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
101 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
[all …]
Dr8a7795-cpg-mssr.c131 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
132 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
133 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
134 DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
135 DEF_MOD("tmu3", 122, R8A7795_CLK_S3D2),
136 DEF_MOD("tmu2", 123, R8A7795_CLK_S3D2),
137 DEF_MOD("tmu1", 124, R8A7795_CLK_S3D2),
138 DEF_MOD("tmu0", 125, R8A7795_CLK_CP),
139 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
140 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
[all …]
Dr8a774e1-cpg-mssr.c127 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
128 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
129 DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
130 DEF_MOD("tmu3", 122, R8A774E1_CLK_S3D2),
131 DEF_MOD("tmu2", 123, R8A774E1_CLK_S3D2),
132 DEF_MOD("tmu1", 124, R8A774E1_CLK_S3D2),
133 DEF_MOD("tmu0", 125, R8A774E1_CLK_CP),
134 DEF_MOD("vcplf", 130, R8A774E1_CLK_S2D1),
135 DEF_MOD("vdpb", 131, R8A774E1_CLK_S2D1),
136 DEF_MOD("scif5", 202, R8A774E1_CLK_S3D4),
[all …]
Dr8a7745-cpg-mssr.c81 DEF_MOD("msiof0", 0, R8A7745_CLK_MP),
82 DEF_MOD("vcp0", 101, R8A7745_CLK_ZS),
83 DEF_MOD("vpc0", 103, R8A7745_CLK_ZS),
84 DEF_MOD("tmu1", 111, R8A7745_CLK_P),
85 DEF_MOD("3dg", 112, R8A7745_CLK_ZG),
86 DEF_MOD("2d-dmac", 115, R8A7745_CLK_ZS),
87 DEF_MOD("fdp1-0", 119, R8A7745_CLK_ZS),
88 DEF_MOD("tmu3", 121, R8A7745_CLK_P),
89 DEF_MOD("tmu2", 122, R8A7745_CLK_P),
90 DEF_MOD("cmt0", 124, R8A7745_CLK_R),
[all …]
Dr8a7794-cpg-mssr.c87 DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
88 DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
89 DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
90 DEF_MOD("jpu", 106, R8A7794_CLK_M2),
91 DEF_MOD("tmu1", 111, R8A7794_CLK_P),
92 DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
93 DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
94 DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
95 DEF_MOD("tmu3", 121, R8A7794_CLK_P),
96 DEF_MOD("tmu2", 122, R8A7794_CLK_P),
[all …]
Dr8a774a1-cpg-mssr.c126 DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
127 DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
128 DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
129 DEF_MOD("tmu1", 124, R8A774A1_CLK_S3D2),
130 DEF_MOD("tmu0", 125, R8A774A1_CLK_CP),
131 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
132 DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
133 DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
134 DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4),
135 DEF_MOD("scif1", 206, R8A774A1_CLK_S3D4),
[all …]
Dr8a774b1-cpg-mssr.c123 DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
124 DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
125 DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
126 DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
127 DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
128 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
129 DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
130 DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
131 DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
132 DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4),
[all …]
Dr8a77990-cpg-mssr.c136 DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
137 DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
138 DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
139 DEF_MOD("tmu1", 124, R8A77990_CLK_S3D2C),
140 DEF_MOD("tmu0", 125, R8A77990_CLK_CP),
141 DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
142 DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
143 DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
144 DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
145 DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
[all …]
Dr8a77470-cpg-mssr.c77 DEF_MOD("msiof0", 0, R8A77470_CLK_MP),
78 DEF_MOD("vcp0", 101, R8A77470_CLK_ZS),
79 DEF_MOD("vpc0", 103, R8A77470_CLK_ZS),
80 DEF_MOD("tmu1", 111, R8A77470_CLK_P),
81 DEF_MOD("3dg", 112, R8A77470_CLK_ZS),
82 DEF_MOD("2d-dmac", 115, R8A77470_CLK_ZS),
83 DEF_MOD("fdp1-0", 119, R8A77470_CLK_ZS),
84 DEF_MOD("tmu3", 121, R8A77470_CLK_P),
85 DEF_MOD("tmu2", 122, R8A77470_CLK_P),
86 DEF_MOD("cmt0", 124, R8A77470_CLK_R),
[all …]
Dr8a774c0-cpg-mssr.c135 DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C),
136 DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C),
137 DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C),
138 DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C),
139 DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
140 DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
141 DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
142 DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
143 DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C),
144 DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C),
[all …]
Dr8a779a0-cpg-mssr.c136 DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
137 DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
138 DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
139 DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
140 DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
141 DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2),
142 DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD),
143 DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0),
144 DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0),
145 DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0),
[all …]
Dr8a7792-cpg-mssr.c80 DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
81 DEF_MOD("jpu", 106, R8A7792_CLK_M2),
82 DEF_MOD("tmu1", 111, R8A7792_CLK_P),
83 DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
84 DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
85 DEF_MOD("tmu3", 121, R8A7792_CLK_P),
86 DEF_MOD("tmu2", 122, R8A7792_CLK_P),
87 DEF_MOD("cmt0", 124, R8A7792_CLK_R),
88 DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
89 DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
[all …]
Dr8a77995-cpg-mssr.c122 DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
123 DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
124 DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
125 DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
126 DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
127 DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
128 DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
129 DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
130 DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
131 DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
[all …]
Dr8a77980-cpg-mssr.c115 DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
116 DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
117 DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
118 DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
119 DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
120 DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
121 DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
122 DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
123 DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
124 DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
[all …]
Dr8a77970-cpg-mssr.c110 DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
111 DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
112 DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
113 DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
114 DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
115 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
116 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
117 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
118 DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
119 DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
[all …]
Dr9a07g044-cpg.c191 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
193 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
195 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
197 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
199 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
201 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
203 DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
205 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
207 DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
209 DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
[all …]
Dr9a07g043-cpg.c134 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
136 DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
138 DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
142 DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
144 DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
147 DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
149 DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
151 DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
153 DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
155 DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
[all …]
Dr8a779f0-cpg-mssr.c129 DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3),
130 DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3),
131 DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3),
132 DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3),
133 DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
134 DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
135 DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
136 DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
137 DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
138 DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
[all …]
Dr8a779g0-cpg-mssr.c158 DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
159 DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
160 DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
161 DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
162 DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
163 DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
164 DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1),
165 DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER),
166 DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER),
167 DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER),
[all …]
Dr9a09g011-cpg.c129 DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
130 DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
133 DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
134 DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
135 DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12),
136 DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12),
137 DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
138 DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
139 DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
140 DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
[all …]

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