Searched refs:Counter (Results 1 – 25 of 61) sorted by relevance
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19 typedef u_long Counter ; typedef29 Counter count ;195 Counter fddiMACFrame_Ct ;196 Counter fddiMACCopied_Ct ;197 Counter fddiMACTransmit_Ct ;198 Counter fddiMACToken_Ct ;199 Counter fddiMACError_Ct ;200 Counter fddiMACLost_Ct ;201 Counter fddiMACTvxExpired_Ct ;202 Counter fddiMACNotCopied_Ct ;[all …]
4 Generic Counter Interface10 Counter devices are prevalent among a diverse spectrum of industries.15 Generic Counter interface enables drivers to support and expose a common21 Counter devices can vary greatly in design, but regardless of whether25 the Generic Counter interface.45 When the Signal data is available for user access, the Generic Counter64 count data. The Generic Counter interface provides the following83 context of the Generic Counter interface, a counter consists of Counts94 Counter interface represents the count data as a natural number.97 for the count data. The Generic Counter interface provides the following[all …]
3 # Counter devices7 tristate "Counter support"9 This enables counter device support through the Generic Counter84 tristate "Microchip Timer Counter Capture driver"88 Select this option to enable the Microchip Timer Counter Block
153 - CTR (Counter) mode (NIST SP800-38A)170 - CTR (Counter) mode (NIST SP800-38A)201 - CTR (Counter) mode (NIST SP800-38A)233 - CTR (Counter) mode (NIST SP800-38A)250 - CTR (Counter) mode (NIST SP800-38A)264 CCM (Counter with Cipher Block Chaining-Message Authentication Code)
12 The Counter Enable signal CNT_EN is used54 | Prescaler +-> | Counter | +-> | Master | TRGO(2)119 Counter is always ON.
50 whether Replay Protected Monotonic Counter support has been enabled.61 whether an Replay Protected Monotonic Counter supported SPI is installed
256 Size of the Counter events queue in number of struct265 the Counter. This should match the name of the device as it273 belonging to the Counter.280 belonging to the Counter.
1 OMAP Counter-32K bindings
1 * Cirrus Logic CLPS711X Timer Counter
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
51 /* 64-bit Global Free Running Counter */
26 load_mem_type_cnt = collections.Counter()
72 by configuring BDF to "bdf". Counter only counts the bandwidth of message96 Counter counts when TLP length within the specified range. You can set the
11 is one register for each counter. Counter 0 is special in that it always counts
26 - Group 0: PMU Cycle Counter. This group has one pair of counters
30 - Counter value for the rpmb device will be read to stdout.
14 CR 0 (Recovery Counter) used for ptrace81 R (Recovery Counter trap) 0
83 Support the clocks of the Timer/Counter Unit (TCU) of the Ingenic
177 - CTR (Counter) mode (NIST SP800-38A)198 - CTR (Counter) mode (NIST SP800-38A)
29 [Fixed Counter: Counts the number of instructions retired. Unit: cpu_atom]31 [Number of instructions retired. Fixed Counter - architectural event. Unit: cpu_core]
29 14 counter Counter
668 tristate "CTR (Counter)"672 CTR (Counter) mode (NIST SP800-38A)760 XCTR (XOR Counter) mode for HCTR2817 tristate "CCM (Counter with Cipher Block Chaining-MAC)"823 CCM (Counter with Cipher Block Chaining-Message Authentication Code)827 tristate "GCM (Galois/Counter Mode) and GMAC (GCM MAC)"834 GCM (Galois/Counter Mode) authenticated encryption mode and GMAC
168 Bit 3 = Counter 2169 Bit 2 = Counter 1170 Bit 1 = Counter 0175 Bit 3 = Counter 2176 Bit 2 = Counter 1177 Bit 1 = Counter 0
25 amounts of time (with interrupts disabled), polling the CPU Time Stamp Counter
159 bool "Timer Counter Blocks (TCB) support"
