Searched refs:Clock (Results 1 – 25 of 270) sorted by relevance
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3 # MediaTek Clock Drivers5 menu "Clock driver for MediaTek SoC"15 bool "Clock driver for MediaTek MT2701"23 bool "Clock driver for MediaTek MT2701 mmsys"29 bool "Clock driver for MediaTek MT2701 imgsys"35 bool "Clock driver for MediaTek MT2701 vdecsys"41 bool "Clock driver for MediaTek MT2701 hifsys"47 bool "Clock driver for MediaTek MT2701 ethsys"53 bool "Clock driver for MediaTek MT2701 bdpsys"59 bool "Clock driver for Mediatek MT2701 audsys"[all …]
67 tristate "IMX8MM CCM Clock Driver"71 Build the driver for i.MX8MM CCM Clock Driver74 tristate "IMX8MN CCM Clock Driver"78 Build the driver for i.MX8MN CCM Clock Driver81 tristate "IMX8MP CCM Clock Driver"85 Build the driver for i.MX8MP CCM Clock Driver88 tristate "IMX8MQ CCM Clock Driver"92 Build the driver for i.MX8MQ CCM Clock Driver95 tristate "IMX8QXP SCU Clock"103 tristate "IMX8ULP CCM Clock Driver"[all …]
40 tristate "MSM8916 APCS Clock Controller"43 Support for the APCS Clock Controller on msm8916 devices. The49 tristate "MSM8996 CPU Clock Controller"58 tristate "SDX55 and SDX65 APCS Clock Controller"61 Support for the APCS Clock Controller on SDX55, SDX65 platforms. The67 tristate "RPM based Clock Controller"80 tristate "RPM over SMD based Clock Controller"93 tristate "RPMh Clock Driver"102 tristate "APQ8084 Global Clock Controller"110 tristate "APQ8084 Multimedia Clock Controller"[all …]
17 Build the driver for PX30 Clock Driver.24 Build the driver for RV110x Clock Driver.31 Build the driver for RV1126 Clock Driver.38 Build the driver for RK3036 Clock Driver.45 Build the driver for RK312x Clock Driver.52 Build the driver for RK3188 Clock Driver.59 Build the driver for RK322x Clock Driver.66 Build the driver for RK3288 Clock Driver.73 Build the driver for RK3308 Clock Driver.80 Build the driver for RK3328 Clock Driver.[all …]
22 bool "Common Clock Framework"38 tristate "Clock driver for WM831x/2x PMICs"55 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"60 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs63 tristate "Clock driver for Apple SoC NCOs"72 tristate "Clock driver for Maxim 77620/77686/77802 MFD"79 tristate "Maxim 9485 Programmable Clock Generator"82 This driver supports Maxim 9485 Programmable Audio Clock Generator85 tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"93 tristate "Clock driver for Hi655x" if EXPERT[all …]
3 tristate "HI3516CV300 Clock Driver"11 tristate "Hi3519 Clock Driver"19 bool "Hi3559A Clock Driver"27 bool "Hi3660 Clock Driver"34 bool "Hi3670 Clock Driver"41 tristate "Hi3798CV200 Clock Driver"49 bool "Hi6220 Clock Driver"63 bool "Hi6220 Stub Clock Driver" if EXPERT71 bool "Hi3660 Stub Clock Driver" if EXPERT
34 * PCLK: Pixel Clock35 * SYMCLK: Symbol Clock36 * SOCCLK: GPU Engine Clock37 * DISPCLK: Display Clock38 * DPPCLK: DPP Clock39 * DCFCLK: Display Controller Fabric Clock40 * REFCLK: Real Time Reference Clock42 * FCLK: Fabric Clock43 * MCLK: Memory Clock83 Display Clock Generator block
1 * Gated Clock bindings for Marvell EBU SoCs11 ID Clock Peripheral14 1 pex0_en PCIe 0 Clock out15 2 pex1_en PCIe 1 Clock out28 ID Clock Peripheral33 5 pex0 PCIe 0 Clock out34 6 pex1 PCIe 1 Clock out55 ID Clock Peripheral82 ID Clock Peripheral96 ID Clock Peripheral[all …]
9 ID Clock18 - reg : shall be the register address of the Core PLL and Clock Divider20 Core PLL and Clock Divider Control 1 register. Thus, it will have
1 * Core Clock bindings for Marvell MVEBU SoCs30 3 = hclk (SDRAM Controller Internal Clock)31 4 = dclk (SDRAM Interface Clock)32 5 = refclk (Reference Clock)38 3 = mpll (MPLL Clock)
1 * Peripheral Clock bindings for Marvell Armada 37xx SoCs13 ID Clock name Description34 ID Clock name Description56 - reg : must be the register address of North/South Bridge Clock register
1 Device Tree Clock bindings for the Zynq 7000 EPP9 == Clock Controller ==31 Clock inputs:40 Clock outputs:
1 * Actions Semi Owl Clock Management Unit (CMU)3 The Actions Semi Owl Clock Management Unit generates and supplies clock34 Example: Clock Management Unit node:
1 Device Tree Clock bindings for arch-at917 Slow Clock controller:15 at91 SCKC (Slow Clock Controller)
1 Alphascale Clock Controller3 The ACC (Alphascale Clock Controller) is responsible of choising proper107 Clock consumer with only one, _AHB_ sink.
3 menu "Clock driver for ARM Reference designs"8 bool "Clock driver for ARM Reference designs ICST"16 bool "Clock driver for ARM SP810 System Controller"23 tristate "Clock driver for Versatile Express OSC clock generators"
129 | 0 | M0H | JOY0DAT Horizontal Clock |131 | 1 | M0HQ | JOY0DAT Horizontal Clock (quadrature) |133 | 2 | M0V | JOY0DAT Vertical Clock |135 | 3 | M0VQ | JOY0DAT Vertical Clock (quadrature) |137 | 4 | M1V | JOY1DAT Horizontal Clock |139 | 5 | M1VQ | JOY1DAT Horizontal Clock (quadrature) |141 | 6 | M1V | JOY1DAT Vertical Clock |143 | 7 | M1VQ | JOY1DAT Vertical Clock (quadrature) |
3 # MediaTek Mt7621 Clock Driver6 bool "Clock driver for MediaTek MT7621"
5 bool "Clock driver for Lightning Mountain(LGM) platform"7 Clock Generation Unit(CGU) driver for Intel Lightning Mountain(LGM)
5 # Clock Distribution device drivers12 menu "Clock Generator/Distribution"15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"19 Clock Generator. The driver provides direct access via sysfs.
121 * System Clock -- suspended !!!!123 * Name -- "System Clock Mode"131 Clock-source controller, which is a kind of ALSA-standard. I135 Clock-source-controller instead !!!!137 * Clock Source 139 * Name -- "Sample Clock Source"298 * Word Clock Sync Status300 * Name -- "Word Clock Lock Status"306 Word Clock Input is 0=Unlocked, 1=Locked, or 2=Synced.
1 * APM X-Gene Real Time Clock3 RTC controller for the APM X-Gene Real Time Clock
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
5 Description: Attribute for calibrating ST-Ericsson AB8500 Real Time Clock7 calibrate the AB8500.s 32KHz Real Time Clock.
9 Master Clock24 The Digital Audio Interface is usually driven by a Bit Clock (often referred to32 Bit Clock can be generated as follows:-
