Searched refs:CVMX_MIO_QLMX_CFG (Results 1 – 3 of 3) sorted by relevance
103 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_cn68xx()117 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface)); in __cvmx_get_mode_cn68xx()129 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3)); in __cvmx_get_mode_cn68xx()134 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); in __cvmx_get_mode_cn68xx()176 mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); in __cvmx_get_mode_octeon2()178 mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); in __cvmx_get_mode_octeon2()195 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); in __cvmx_get_mode_octeon2()203 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_octeon2()214 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); in __cvmx_get_mode_octeon2()
1173 qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port)); in __cvmx_pcie_rc_initialize_gen2()
103 #define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8) macro
