Searched refs:CLK_TBG_DIV1_MAX (Results 1 – 1 of 1) sorted by relevance
89 #define CLK_TBG_DIV1_MAX 6 macro1135 if (uart_clock_base->div > CLK_TBG_DIV1_MAX) { in mvebu_uart_clock_prepare()1136 d1 = CLK_TBG_DIV1_MAX; in mvebu_uart_clock_prepare()1137 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; in mvebu_uart_clock_prepare()1462 else if (d1 > CLK_TBG_DIV1_MAX) in mvebu_uart_clock_probe()1463 d1 = CLK_TBG_DIV1_MAX; in mvebu_uart_clock_probe()
