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Searched refs:AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT (Results 1 – 18 of 18) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h12178 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
Ddce_11_0_sh_mask.h13442 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
Ddce_10_0_sh_mask.h13436 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
Ddce_11_2_sh_mask.h14058 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 macro
Ddce_12_0_sh_mask.h7017 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_sh_mask.h5799 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_2_1_0_sh_mask.h7557 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_2_1_sh_mask.h5197 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_0_1_sh_mask.h7538 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_1_0_sh_mask.h8152 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_1_5_sh_mask.h6022 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_1_2_sh_mask.h8093 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_0_2_sh_mask.h7367 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_1_6_sh_mask.h8752 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_1_4_sh_mask.h15681 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_0_0_sh_mask.h7470 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_2_0_0_sh_mask.h7825 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro
Ddcn_3_2_0_sh_mask.h5195 #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT … macro