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Searched refs:AMDGPU_GPU_PAGE_ALIGN (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.c257 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_vcn_sw_init()
260 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)); in amdgpu_vcn_sw_init()
263 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)); in amdgpu_vcn_sw_init()
610 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_send_msg()
664 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_create_msg()
699 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr); in amdgpu_vcn_dec_get_destroy_msg()
784 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_dec_sw_send_msg()
928 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_create_msg()
994 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); in amdgpu_vcn_enc_get_destroy_msg()
Damdgpu_gart.h38 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) macro
Damdgpu_uvd.h37 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
Dvcn_v4_0.c353 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume()
396 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_mc_resume()
413 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in vcn_v4_0_mc_resume_dpg_mode()
499 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1218 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v4_0_start_sriov()
1298 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); in vcn_v4_0_start_sriov()
Dvcn_v2_0.c330 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume()
379 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_0_mc_resume()
386 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
473 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1880 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_start_sriov()
Dvcn_v2_5.c397 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume()
446 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v2_5_mc_resume()
452 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume_dpg_mode()
539 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1196 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_sriov_start()
Dvcn_v3_0.c447 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume()
492 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); in vcn_v3_0_mc_resume()
497 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_mc_resume_dpg_mode()
584 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1331 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v3_0_start_sriov()
Damdgpu_vm_pt.c140 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_pt_num_entries(adev, level) * 8); in amdgpu_vm_pt_size()
Damdgpu_vce.c468 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); in amdgpu_vce_get_create_msg()
Dvcn_v1_0.c304 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_spg_mode()
371 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_dpg_mode()
Damdgpu_uvd.c328 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); in amdgpu_uvd_sw_init()
Duvd_v7_0.c816 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v7_0_sriov_start()