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Searched refs:zx_writel (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/zte/
Dzx_plane.c110 zx_writel(zplane->rsz + RSZ_VL_ENABLE_CFG, 1); in zx_vl_rsz_set_update()
156 zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); in zx_vl_rsz_setup()
157 zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); in zx_vl_rsz_setup()
173 zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w)); in zx_vl_rsz_setup()
174 zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h)); in zx_vl_rsz_setup()
175 zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w)); in zx_vl_rsz_setup()
176 zx_writel(rsz + RSZ_VL_CHROMA_VER, rsz_step_value(src_chroma_h, dst_h)); in zx_vl_rsz_setup()
222 zx_writel(paddr_reg, paddr); in zx_vl_plane_atomic_update()
227 zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); in zx_vl_plane_atomic_update()
230 zx_writel(layer + VL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y)); in zx_vl_plane_atomic_update()
[all …]
Dzx_tvenc.c167 zx_writel(tvenc->mmio + VENC_VIDEO_INFO, zmode->video_info); in zx_tvenc_encoder_mode_set()
168 zx_writel(tvenc->mmio + VENC_VIDEO_RES, zmode->video_res); in zx_tvenc_encoder_mode_set()
169 zx_writel(tvenc->mmio + VENC_FIELD1_PARAM, zmode->field1_param); in zx_tvenc_encoder_mode_set()
170 zx_writel(tvenc->mmio + VENC_FIELD2_PARAM, zmode->field2_param); in zx_tvenc_encoder_mode_set()
171 zx_writel(tvenc->mmio + VENC_LINE_O_1, zmode->burst_line_odd1); in zx_tvenc_encoder_mode_set()
172 zx_writel(tvenc->mmio + VENC_LINE_E_1, zmode->burst_line_even1); in zx_tvenc_encoder_mode_set()
173 zx_writel(tvenc->mmio + VENC_LINE_O_2, zmode->burst_line_odd2); in zx_tvenc_encoder_mode_set()
174 zx_writel(tvenc->mmio + VENC_LINE_E_2, zmode->burst_line_even2); in zx_tvenc_encoder_mode_set()
175 zx_writel(tvenc->mmio + VENC_LINE_TIMING_PARAM, in zx_tvenc_encoder_mode_set()
177 zx_writel(tvenc->mmio + VENC_WEIGHT_VALUE, zmode->weight_value); in zx_tvenc_encoder_mode_set()
[all …]
Dzx_vga.c89 zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, 0); in zx_vga_connector_get_modes()
99 zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, in zx_vga_connector_get_modes()
109 zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_HAS_DEVICE); in zx_vga_connector_get_modes()
241 zx_writel(vga->mmio + VGA_SUB_ADDR, offset); in zx_vga_i2c_read()
278 zx_writel(vga->mmio + VGA_DEVICE_ADDR, msg->addr); in zx_vga_i2c_write()
385 zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, in zx_vga_irq_handler()
409 zx_writel(vga->mmio + VGA_CLK_DIV_FS, div); in zx_vga_hw_init()
412 zx_writel(vga->mmio + VGA_AUTO_DETECT_PARA, 0x80); in zx_vga_hw_init()
413 zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_NO_DEVICE); in zx_vga_hw_init()
419 zx_writel(vga->mmio + VGA_DEVICE_ADDR, DDC_ADDR); in zx_vga_hw_init()
Dzx_vou.c349 zx_writel(zcrtc->chnreg + CHN_UPDATE, 1); in vou_chn_set_update()
372 zx_writel(vou->timing + regs->fir_active, val); in zx_crtc_atomic_enable()
377 zx_writel(vou->timing + regs->fir_htiming, val); in zx_crtc_atomic_enable()
382 zx_writel(vou->timing + regs->fir_vtiming, val); in zx_crtc_atomic_enable()
391 zx_writel(vou->timing + SEC_V_ACTIVE, val); in zx_crtc_atomic_enable()
400 zx_writel(vou->timing + regs->sec_vtiming, val); in zx_crtc_atomic_enable()
416 zx_writel(vou->timing + regs->timing_shift, val); in zx_crtc_atomic_enable()
417 zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL); in zx_crtc_atomic_enable()
689 zx_writel(vou->timing + TIMING_INT_STATE, state); in vou_irq_handler()
699 zx_writel(vou->osd + OSD_INT_CLRSTA, state); in vou_irq_handler()
[all …]
Dzx_drm_drv.h20 static inline void zx_writel(void __iomem *reg, u32 val) in zx_writel() function
31 zx_writel(reg, tmp); in zx_writel_mask()