| /Linux-v5.4/drivers/gpu/drm/meson/ |
| D | meson_viu.c | 102 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_g12a_osd1_matrix()
146 writel_bits_relaxed(3 << 30, m[21] << 30, in meson_viu_set_osd_matrix()
148 writel_bits_relaxed(7 << 16, m[22] << 16, in meson_viu_set_osd_matrix()
152 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_osd_matrix()
154 writel_bits_relaxed(BIT(1), 0, in meson_viu_set_osd_matrix()
165 writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0, in meson_viu_set_osd_matrix()
167 writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0, in meson_viu_set_osd_matrix()
218 writel_bits_relaxed(0x7 << 29, 7 << 29, in meson_viu_set_osd_lut()
221 writel_bits_relaxed(0x7 << 29, 0, in meson_viu_set_osd_lut()
245 writel_bits_relaxed(7 << 27, 7 << 27, in meson_viu_set_osd_lut()
[all …]
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| D | meson_vpp.c | 97 writel_bits_relaxed(0xff << 16, 0xff << 16, in meson_vpp_init()
111 writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f, in meson_vpp_init()
118 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, in meson_vpp_init()
122 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, in meson_vpp_init()
126 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | in meson_vpp_init()
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| D | meson_plane.c | 147 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, in meson_plane_atomic_update()
154 writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, in meson_plane_atomic_update()
161 writel_bits_relaxed(OSD_REPLACE_EN, 0, in meson_plane_atomic_update()
168 writel_bits_relaxed(OSD_REPLACE_EN, 0, in meson_plane_atomic_update()
331 writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0, in meson_plane_atomic_disable()
334 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, in meson_plane_atomic_disable()
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| D | meson_dw_hdmi.c | 494 writel_bits_relaxed(0x3, 0, in dw_hdmi_phy_init()
496 writel_bits_relaxed(0xf << 8, 0, in dw_hdmi_phy_init()
506 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), in dw_hdmi_phy_init()
511 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, in dw_hdmi_phy_init()
514 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, in dw_hdmi_phy_init()
689 writel_bits_relaxed(0x3, 0, in meson_venc_hdmi_encoder_disable()
941 writel_bits_relaxed(BIT(15), BIT(15), in meson_dw_hdmi_bind()
943 writel_bits_relaxed(BIT(15), BIT(15), in meson_dw_hdmi_bind()
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| D | meson_crtc.c | 132 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE, in meson_crtc_atomic_enable()
180 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND | in meson_crtc_atomic_disable()
235 writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND, in meson_crtc_enable_osd1()
253 writel_bits_relaxed(3 << 8, 3 << 8, in meson_g12a_crtc_enable_osd1()
259 writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | in meson_crtc_enable_vd1()
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| D | meson_venc_cvbs.c | 174 writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, in meson_venc_cvbs_encoder_enable()
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| D | meson_venc.c | 1041 writel_bits_relaxed(0xff, 0xff, in meson_venc_hdmi_mode_set()
1396 writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH, in meson_venc_hdmi_mode_set()
1777 writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | in meson_venc_init()
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| D | meson_overlay.c | 522 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, in meson_overlay_atomic_disable()
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| D | meson_registers.h | 14 #define writel_bits_relaxed(mask, val, addr) \ macro
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| /Linux-v5.4/drivers/spi/ |
| D | spi-meson-spicc.c | 117 #define writel_bits_relaxed(mask, val, addr) \ macro
230 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, in meson_spicc_setup_burst()
288 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, in meson_spicc_irq()
388 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_transfer_one()
448 writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG); in meson_spicc_prepare_message()
461 writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG); in meson_spicc_unprepare_transfer()
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| /Linux-v5.4/drivers/media/platform/meson/ |
| D | ao-cec.c | 228 #define writel_bits_relaxed(mask, val, addr) \ macro
309 writel_bits_relaxed(cfg, enable ? cfg : 0, in meson_ao_cec_irq_setup()
550 writel_bits_relaxed(CEC_GEN_CNTL_RESET, CEC_GEN_CNTL_RESET, in meson_ao_cec_adap_enable()
557 writel_bits_relaxed(CEC_GEN_CNTL_CLK_CTRL_MASK, in meson_ao_cec_adap_enable()
565 writel_bits_relaxed(CEC_GEN_CNTL_RESET, 0, in meson_ao_cec_adap_enable()
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