1 /*******************************************************************
2  * This file is part of the Emulex Linux Device Driver for         *
3  * Fibre Channel Host Bus Adapters.                                *
4  * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
5  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.  *
6  * Copyright (C) 2009-2016 Emulex.  All rights reserved.           *
7  * EMULEX and SLI are trademarks of Emulex.                        *
8  * www.broadcom.com                                                *
9  *                                                                 *
10  * This program is free software; you can redistribute it and/or   *
11  * modify it under the terms of version 2 of the GNU General       *
12  * Public License as published by the Free Software Foundation.    *
13  * This program is distributed in the hope that it will be useful. *
14  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
15  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
16  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
17  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
19  * more details, a copy of which can be found in the file COPYING  *
20  * included with this package.                                     *
21  *******************************************************************/
22 
23 /* Macros to deal with bit fields. Each bit field must have 3 #defines
24  * associated with it (_SHIFT, _MASK, and _WORD).
25  * EG. For a bit field that is in the 7th bit of the "field4" field of a
26  * structure and is 2 bits in size the following #defines must exist:
27  *	struct temp {
28  *		uint32_t	field1;
29  *		uint32_t	field2;
30  *		uint32_t	field3;
31  *		uint32_t	field4;
32  *	#define example_bit_field_SHIFT		7
33  *	#define example_bit_field_MASK		0x03
34  *	#define example_bit_field_WORD		field4
35  *		uint32_t	field5;
36  *	};
37  * Then the macros below may be used to get or set the value of that field.
38  * EG. To get the value of the bit field from the above example:
39  *	struct temp t1;
40  *	value = bf_get(example_bit_field, &t1);
41  * And then to set that bit field:
42  *	bf_set(example_bit_field, &t1, 2);
43  * Or clear that bit field:
44  *	bf_set(example_bit_field, &t1, 0);
45  */
46 #define bf_get_be32(name, ptr) \
47 	((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
48 #define bf_get_le32(name, ptr) \
49 	((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
50 #define bf_get(name, ptr) \
51 	(((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
52 #define bf_set_le32(name, ptr, value) \
53 	((ptr)->name##_WORD = cpu_to_le32(((((value) & \
54 	name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
55 	~(name##_MASK << name##_SHIFT)))))
56 #define bf_set(name, ptr, value) \
57 	((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
58 		 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
59 
60 struct dma_address {
61 	uint32_t addr_lo;
62 	uint32_t addr_hi;
63 };
64 
65 struct lpfc_sli_intf {
66 	uint32_t word0;
67 #define lpfc_sli_intf_valid_SHIFT		29
68 #define lpfc_sli_intf_valid_MASK		0x00000007
69 #define lpfc_sli_intf_valid_WORD		word0
70 #define LPFC_SLI_INTF_VALID		6
71 #define lpfc_sli_intf_sli_hint2_SHIFT		24
72 #define lpfc_sli_intf_sli_hint2_MASK		0x0000001F
73 #define lpfc_sli_intf_sli_hint2_WORD		word0
74 #define LPFC_SLI_INTF_SLI_HINT2_NONE	0
75 #define lpfc_sli_intf_sli_hint1_SHIFT		16
76 #define lpfc_sli_intf_sli_hint1_MASK		0x000000FF
77 #define lpfc_sli_intf_sli_hint1_WORD		word0
78 #define LPFC_SLI_INTF_SLI_HINT1_NONE	0
79 #define LPFC_SLI_INTF_SLI_HINT1_1	1
80 #define LPFC_SLI_INTF_SLI_HINT1_2	2
81 #define lpfc_sli_intf_if_type_SHIFT		12
82 #define lpfc_sli_intf_if_type_MASK		0x0000000F
83 #define lpfc_sli_intf_if_type_WORD		word0
84 #define LPFC_SLI_INTF_IF_TYPE_0		0
85 #define LPFC_SLI_INTF_IF_TYPE_1		1
86 #define LPFC_SLI_INTF_IF_TYPE_2		2
87 #define LPFC_SLI_INTF_IF_TYPE_6		6
88 #define lpfc_sli_intf_sli_family_SHIFT		8
89 #define lpfc_sli_intf_sli_family_MASK		0x0000000F
90 #define lpfc_sli_intf_sli_family_WORD		word0
91 #define LPFC_SLI_INTF_FAMILY_BE2	0x0
92 #define LPFC_SLI_INTF_FAMILY_BE3	0x1
93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0	0xa
94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0	0xb
95 #define lpfc_sli_intf_slirev_SHIFT		4
96 #define lpfc_sli_intf_slirev_MASK		0x0000000F
97 #define lpfc_sli_intf_slirev_WORD		word0
98 #define LPFC_SLI_INTF_REV_SLI3		3
99 #define LPFC_SLI_INTF_REV_SLI4		4
100 #define lpfc_sli_intf_func_type_SHIFT		0
101 #define lpfc_sli_intf_func_type_MASK		0x00000001
102 #define lpfc_sli_intf_func_type_WORD		word0
103 #define LPFC_SLI_INTF_IF_TYPE_PHYS	0
104 #define LPFC_SLI_INTF_IF_TYPE_VIRT	1
105 };
106 
107 #define LPFC_SLI4_MBX_EMBED	true
108 #define LPFC_SLI4_MBX_NEMBED	false
109 
110 #define LPFC_SLI4_MB_WORD_COUNT		64
111 #define LPFC_MAX_MQ_PAGE		8
112 #define LPFC_MAX_WQ_PAGE_V0		4
113 #define LPFC_MAX_WQ_PAGE		8
114 #define LPFC_MAX_RQ_PAGE		8
115 #define LPFC_MAX_CQ_PAGE		4
116 #define LPFC_MAX_EQ_PAGE		8
117 
118 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
119 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
120 #define LPFC_VFR_PAGE_SIZE	0x1000 /* 4KB BAR2 per-VF register page size */
121 
122 /* Define SLI4 Alignment requirements. */
123 #define LPFC_ALIGN_16_BYTE	16
124 #define LPFC_ALIGN_64_BYTE	64
125 
126 /* Define SLI4 specific definitions. */
127 #define LPFC_MQ_CQE_BYTE_OFFSET	256
128 #define LPFC_MBX_CMD_HDR_LENGTH 16
129 #define LPFC_MBX_ERROR_RANGE	0x4000
130 #define LPFC_BMBX_BIT1_ADDR_HI	0x2
131 #define LPFC_BMBX_BIT1_ADDR_LO	0
132 #define LPFC_RPI_HDR_COUNT	64
133 #define LPFC_HDR_TEMPLATE_SIZE	4096
134 #define LPFC_RPI_ALLOC_ERROR 	0xFFFF
135 #define LPFC_FCF_RECORD_WD_CNT	132
136 #define LPFC_ENTIRE_FCF_DATABASE 0
137 #define LPFC_DFLT_FCF_INDEX	 0
138 
139 /* Virtual function numbers */
140 #define LPFC_VF0		0
141 #define LPFC_VF1		1
142 #define LPFC_VF2		2
143 #define LPFC_VF3		3
144 #define LPFC_VF4		4
145 #define LPFC_VF5		5
146 #define LPFC_VF6		6
147 #define LPFC_VF7		7
148 #define LPFC_VF8		8
149 #define LPFC_VF9		9
150 #define LPFC_VF10		10
151 #define LPFC_VF11		11
152 #define LPFC_VF12		12
153 #define LPFC_VF13		13
154 #define LPFC_VF14		14
155 #define LPFC_VF15		15
156 #define LPFC_VF16		16
157 #define LPFC_VF17		17
158 #define LPFC_VF18		18
159 #define LPFC_VF19		19
160 #define LPFC_VF20		20
161 #define LPFC_VF21		21
162 #define LPFC_VF22		22
163 #define LPFC_VF23		23
164 #define LPFC_VF24		24
165 #define LPFC_VF25		25
166 #define LPFC_VF26		26
167 #define LPFC_VF27		27
168 #define LPFC_VF28		28
169 #define LPFC_VF29		29
170 #define LPFC_VF30		30
171 #define LPFC_VF31		31
172 
173 /* PCI function numbers */
174 #define LPFC_PCI_FUNC0		0
175 #define LPFC_PCI_FUNC1		1
176 #define LPFC_PCI_FUNC2		2
177 #define LPFC_PCI_FUNC3		3
178 #define LPFC_PCI_FUNC4		4
179 
180 /* SLI4 interface type-2 PDEV_CTL register */
181 #define LPFC_CTL_PDEV_CTL_OFFSET	0x414
182 #define LPFC_CTL_PDEV_CTL_DRST		0x00000001
183 #define LPFC_CTL_PDEV_CTL_FRST		0x00000002
184 #define LPFC_CTL_PDEV_CTL_DD		0x00000004
185 #define LPFC_CTL_PDEV_CTL_LC		0x00000008
186 #define LPFC_CTL_PDEV_CTL_FRL_ALL	0x00
187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE	0x10
188 #define LPFC_CTL_PDEV_CTL_FRL_NIC	0x20
189 #define LPFC_CTL_PDEV_CTL_DDL_RAS	0x1000000
190 
191 #define LPFC_FW_DUMP_REQUEST    (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
192 
193 /* Active interrupt test count */
194 #define LPFC_ACT_INTR_CNT	4
195 
196 /* Algrithmns for scheduling FCP commands to WQs */
197 #define	LPFC_FCP_SCHED_BY_HDWQ		0
198 #define	LPFC_FCP_SCHED_BY_CPU		1
199 
200 /* Algrithmns for NameServer Query after RSCN */
201 #define LPFC_NS_QUERY_GID_FT	0
202 #define LPFC_NS_QUERY_GID_PT	1
203 
204 /* Delay Multiplier constant */
205 #define LPFC_DMULT_CONST       651042
206 #define LPFC_DMULT_MAX         1023
207 
208 /* Configuration of Interrupts / sec for entire HBA port */
209 #define LPFC_MIN_IMAX          5000
210 #define LPFC_MAX_IMAX          5000000
211 #define LPFC_DEF_IMAX          0
212 
213 #define LPFC_IMAX_THRESHOLD    1000
214 #define LPFC_MAX_AUTO_EQ_DELAY 120
215 #define LPFC_EQ_DELAY_STEP     15
216 #define LPFC_EQD_ISR_TRIGGER   20000
217 /* 1s intervals */
218 #define LPFC_EQ_DELAY_MSECS    1000
219 
220 #define LPFC_MIN_CPU_MAP       0
221 #define LPFC_MAX_CPU_MAP       1
222 #define LPFC_HBA_CPU_MAP       1
223 
224 /* PORT_CAPABILITIES constants. */
225 #define LPFC_MAX_SUPPORTED_PAGES	8
226 
227 struct ulp_bde64 {
228 	union ULP_BDE_TUS {
229 		uint32_t w;
230 		struct {
231 #ifdef __BIG_ENDIAN_BITFIELD
232 			uint32_t bdeFlags:8;	/* BDE Flags 0 IS A SUPPORTED
233 						   VALUE !! */
234 			uint32_t bdeSize:24;	/* Size of buffer (in bytes) */
235 #else	/*  __LITTLE_ENDIAN_BITFIELD */
236 			uint32_t bdeSize:24;	/* Size of buffer (in bytes) */
237 			uint32_t bdeFlags:8;	/* BDE Flags 0 IS A SUPPORTED
238 						   VALUE !! */
239 #endif
240 #define BUFF_TYPE_BDE_64    0x00	/* BDE (Host_resident) */
241 #define BUFF_TYPE_BDE_IMMED 0x01	/* Immediate Data BDE */
242 #define BUFF_TYPE_BDE_64P   0x02	/* BDE (Port-resident) */
243 #define BUFF_TYPE_BDE_64I   0x08	/* Input BDE (Host-resident) */
244 #define BUFF_TYPE_BDE_64IP  0x0A	/* Input BDE (Port-resident) */
245 #define BUFF_TYPE_BLP_64    0x40	/* BLP (Host-resident) */
246 #define BUFF_TYPE_BLP_64P   0x42	/* BLP (Port-resident) */
247 		} f;
248 	} tus;
249 	uint32_t addrLow;
250 	uint32_t addrHigh;
251 };
252 
253 /* Maximun size of immediate data that can fit into a 128 byte WQE */
254 #define LPFC_MAX_BDE_IMM_SIZE	64
255 
256 struct lpfc_sli4_flags {
257 	uint32_t word0;
258 #define lpfc_idx_rsrc_rdy_SHIFT		0
259 #define lpfc_idx_rsrc_rdy_MASK		0x00000001
260 #define lpfc_idx_rsrc_rdy_WORD		word0
261 #define LPFC_IDX_RSRC_RDY		1
262 #define lpfc_rpi_rsrc_rdy_SHIFT		1
263 #define lpfc_rpi_rsrc_rdy_MASK		0x00000001
264 #define lpfc_rpi_rsrc_rdy_WORD		word0
265 #define LPFC_RPI_RSRC_RDY		1
266 #define lpfc_vpi_rsrc_rdy_SHIFT		2
267 #define lpfc_vpi_rsrc_rdy_MASK		0x00000001
268 #define lpfc_vpi_rsrc_rdy_WORD		word0
269 #define LPFC_VPI_RSRC_RDY		1
270 #define lpfc_vfi_rsrc_rdy_SHIFT		3
271 #define lpfc_vfi_rsrc_rdy_MASK		0x00000001
272 #define lpfc_vfi_rsrc_rdy_WORD		word0
273 #define LPFC_VFI_RSRC_RDY		1
274 };
275 
276 struct sli4_bls_rsp {
277 	uint32_t word0_rsvd;      /* Word0 must be reserved */
278 	uint32_t word1;
279 #define lpfc_abts_orig_SHIFT      0
280 #define lpfc_abts_orig_MASK       0x00000001
281 #define lpfc_abts_orig_WORD       word1
282 #define LPFC_ABTS_UNSOL_RSP       1
283 #define LPFC_ABTS_UNSOL_INT       0
284 	uint32_t word2;
285 #define lpfc_abts_rxid_SHIFT      0
286 #define lpfc_abts_rxid_MASK       0x0000FFFF
287 #define lpfc_abts_rxid_WORD       word2
288 #define lpfc_abts_oxid_SHIFT      16
289 #define lpfc_abts_oxid_MASK       0x0000FFFF
290 #define lpfc_abts_oxid_WORD       word2
291 	uint32_t word3;
292 #define lpfc_vndr_code_SHIFT	0
293 #define lpfc_vndr_code_MASK	0x000000FF
294 #define lpfc_vndr_code_WORD	word3
295 #define lpfc_rsn_expln_SHIFT	8
296 #define lpfc_rsn_expln_MASK	0x000000FF
297 #define lpfc_rsn_expln_WORD	word3
298 #define lpfc_rsn_code_SHIFT	16
299 #define lpfc_rsn_code_MASK	0x000000FF
300 #define lpfc_rsn_code_WORD	word3
301 
302 	uint32_t word4;
303 	uint32_t word5_rsvd;	/* Word5 must be reserved */
304 };
305 
306 /* event queue entry structure */
307 struct lpfc_eqe {
308 	uint32_t word0;
309 #define lpfc_eqe_resource_id_SHIFT	16
310 #define lpfc_eqe_resource_id_MASK	0x0000FFFF
311 #define lpfc_eqe_resource_id_WORD	word0
312 #define lpfc_eqe_minor_code_SHIFT	4
313 #define lpfc_eqe_minor_code_MASK	0x00000FFF
314 #define lpfc_eqe_minor_code_WORD	word0
315 #define lpfc_eqe_major_code_SHIFT	1
316 #define lpfc_eqe_major_code_MASK	0x00000007
317 #define lpfc_eqe_major_code_WORD	word0
318 #define lpfc_eqe_valid_SHIFT		0
319 #define lpfc_eqe_valid_MASK		0x00000001
320 #define lpfc_eqe_valid_WORD		word0
321 };
322 
323 /* completion queue entry structure (common fields for all cqe types) */
324 struct lpfc_cqe {
325 	uint32_t reserved0;
326 	uint32_t reserved1;
327 	uint32_t reserved2;
328 	uint32_t word3;
329 #define lpfc_cqe_valid_SHIFT		31
330 #define lpfc_cqe_valid_MASK		0x00000001
331 #define lpfc_cqe_valid_WORD		word3
332 #define lpfc_cqe_code_SHIFT		16
333 #define lpfc_cqe_code_MASK		0x000000FF
334 #define lpfc_cqe_code_WORD		word3
335 };
336 
337 /* Completion Queue Entry Status Codes */
338 #define CQE_STATUS_SUCCESS		0x0
339 #define CQE_STATUS_FCP_RSP_FAILURE	0x1
340 #define CQE_STATUS_REMOTE_STOP		0x2
341 #define CQE_STATUS_LOCAL_REJECT		0x3
342 #define CQE_STATUS_NPORT_RJT		0x4
343 #define CQE_STATUS_FABRIC_RJT		0x5
344 #define CQE_STATUS_NPORT_BSY		0x6
345 #define CQE_STATUS_FABRIC_BSY		0x7
346 #define CQE_STATUS_INTERMED_RSP		0x8
347 #define CQE_STATUS_LS_RJT		0x9
348 #define CQE_STATUS_CMD_REJECT		0xb
349 #define CQE_STATUS_FCP_TGT_LENCHECK	0xc
350 #define CQE_STATUS_NEED_BUFF_ENTRY	0xf
351 #define CQE_STATUS_DI_ERROR		0x16
352 
353 /* Used when mapping CQE status to IOCB */
354 #define LPFC_IOCB_STATUS_MASK		0xf
355 
356 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
357 #define CQE_HW_STATUS_NO_ERR		0x0
358 #define CQE_HW_STATUS_UNDERRUN		0x1
359 #define CQE_HW_STATUS_OVERRUN		0x2
360 
361 /* Completion Queue Entry Codes */
362 #define CQE_CODE_COMPL_WQE		0x1
363 #define CQE_CODE_RELEASE_WQE		0x2
364 #define CQE_CODE_RECEIVE		0x4
365 #define CQE_CODE_XRI_ABORTED		0x5
366 #define CQE_CODE_RECEIVE_V1		0x9
367 #define CQE_CODE_NVME_ERSP		0xd
368 
369 /*
370  * Define mask value for xri_aborted and wcqe completed CQE extended status.
371  * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
372  */
373 #define WCQE_PARAM_MASK		0x1FF
374 
375 /* completion queue entry for wqe completions */
376 struct lpfc_wcqe_complete {
377 	uint32_t word0;
378 #define lpfc_wcqe_c_request_tag_SHIFT	16
379 #define lpfc_wcqe_c_request_tag_MASK	0x0000FFFF
380 #define lpfc_wcqe_c_request_tag_WORD	word0
381 #define lpfc_wcqe_c_status_SHIFT	8
382 #define lpfc_wcqe_c_status_MASK		0x000000FF
383 #define lpfc_wcqe_c_status_WORD		word0
384 #define lpfc_wcqe_c_hw_status_SHIFT	0
385 #define lpfc_wcqe_c_hw_status_MASK	0x000000FF
386 #define lpfc_wcqe_c_hw_status_WORD	word0
387 #define lpfc_wcqe_c_ersp0_SHIFT		0
388 #define lpfc_wcqe_c_ersp0_MASK		0x0000FFFF
389 #define lpfc_wcqe_c_ersp0_WORD		word0
390 	uint32_t total_data_placed;
391 	uint32_t parameter;
392 #define lpfc_wcqe_c_bg_edir_SHIFT	5
393 #define lpfc_wcqe_c_bg_edir_MASK	0x00000001
394 #define lpfc_wcqe_c_bg_edir_WORD	parameter
395 #define lpfc_wcqe_c_bg_tdpv_SHIFT	3
396 #define lpfc_wcqe_c_bg_tdpv_MASK	0x00000001
397 #define lpfc_wcqe_c_bg_tdpv_WORD	parameter
398 #define lpfc_wcqe_c_bg_re_SHIFT		2
399 #define lpfc_wcqe_c_bg_re_MASK		0x00000001
400 #define lpfc_wcqe_c_bg_re_WORD		parameter
401 #define lpfc_wcqe_c_bg_ae_SHIFT		1
402 #define lpfc_wcqe_c_bg_ae_MASK		0x00000001
403 #define lpfc_wcqe_c_bg_ae_WORD		parameter
404 #define lpfc_wcqe_c_bg_ge_SHIFT		0
405 #define lpfc_wcqe_c_bg_ge_MASK		0x00000001
406 #define lpfc_wcqe_c_bg_ge_WORD		parameter
407 	uint32_t word3;
408 #define lpfc_wcqe_c_valid_SHIFT		lpfc_cqe_valid_SHIFT
409 #define lpfc_wcqe_c_valid_MASK		lpfc_cqe_valid_MASK
410 #define lpfc_wcqe_c_valid_WORD		lpfc_cqe_valid_WORD
411 #define lpfc_wcqe_c_xb_SHIFT		28
412 #define lpfc_wcqe_c_xb_MASK		0x00000001
413 #define lpfc_wcqe_c_xb_WORD		word3
414 #define lpfc_wcqe_c_pv_SHIFT		27
415 #define lpfc_wcqe_c_pv_MASK		0x00000001
416 #define lpfc_wcqe_c_pv_WORD		word3
417 #define lpfc_wcqe_c_priority_SHIFT	24
418 #define lpfc_wcqe_c_priority_MASK	0x00000007
419 #define lpfc_wcqe_c_priority_WORD	word3
420 #define lpfc_wcqe_c_code_SHIFT		lpfc_cqe_code_SHIFT
421 #define lpfc_wcqe_c_code_MASK		lpfc_cqe_code_MASK
422 #define lpfc_wcqe_c_code_WORD		lpfc_cqe_code_WORD
423 #define lpfc_wcqe_c_sqhead_SHIFT	0
424 #define lpfc_wcqe_c_sqhead_MASK		0x0000FFFF
425 #define lpfc_wcqe_c_sqhead_WORD		word3
426 };
427 
428 /* completion queue entry for wqe release */
429 struct lpfc_wcqe_release {
430 	uint32_t reserved0;
431 	uint32_t reserved1;
432 	uint32_t word2;
433 #define lpfc_wcqe_r_wq_id_SHIFT		16
434 #define lpfc_wcqe_r_wq_id_MASK		0x0000FFFF
435 #define lpfc_wcqe_r_wq_id_WORD		word2
436 #define lpfc_wcqe_r_wqe_index_SHIFT	0
437 #define lpfc_wcqe_r_wqe_index_MASK	0x0000FFFF
438 #define lpfc_wcqe_r_wqe_index_WORD	word2
439 	uint32_t word3;
440 #define lpfc_wcqe_r_valid_SHIFT		lpfc_cqe_valid_SHIFT
441 #define lpfc_wcqe_r_valid_MASK		lpfc_cqe_valid_MASK
442 #define lpfc_wcqe_r_valid_WORD		lpfc_cqe_valid_WORD
443 #define lpfc_wcqe_r_code_SHIFT		lpfc_cqe_code_SHIFT
444 #define lpfc_wcqe_r_code_MASK		lpfc_cqe_code_MASK
445 #define lpfc_wcqe_r_code_WORD		lpfc_cqe_code_WORD
446 };
447 
448 struct sli4_wcqe_xri_aborted {
449 	uint32_t word0;
450 #define lpfc_wcqe_xa_status_SHIFT		8
451 #define lpfc_wcqe_xa_status_MASK		0x000000FF
452 #define lpfc_wcqe_xa_status_WORD		word0
453 	uint32_t parameter;
454 	uint32_t word2;
455 #define lpfc_wcqe_xa_remote_xid_SHIFT	16
456 #define lpfc_wcqe_xa_remote_xid_MASK	0x0000FFFF
457 #define lpfc_wcqe_xa_remote_xid_WORD	word2
458 #define lpfc_wcqe_xa_xri_SHIFT		0
459 #define lpfc_wcqe_xa_xri_MASK		0x0000FFFF
460 #define lpfc_wcqe_xa_xri_WORD		word2
461 	uint32_t word3;
462 #define lpfc_wcqe_xa_valid_SHIFT	lpfc_cqe_valid_SHIFT
463 #define lpfc_wcqe_xa_valid_MASK		lpfc_cqe_valid_MASK
464 #define lpfc_wcqe_xa_valid_WORD		lpfc_cqe_valid_WORD
465 #define lpfc_wcqe_xa_ia_SHIFT		30
466 #define lpfc_wcqe_xa_ia_MASK		0x00000001
467 #define lpfc_wcqe_xa_ia_WORD		word3
468 #define CQE_XRI_ABORTED_IA_REMOTE	0
469 #define CQE_XRI_ABORTED_IA_LOCAL	1
470 #define lpfc_wcqe_xa_br_SHIFT		29
471 #define lpfc_wcqe_xa_br_MASK		0x00000001
472 #define lpfc_wcqe_xa_br_WORD		word3
473 #define CQE_XRI_ABORTED_BR_BA_ACC	0
474 #define CQE_XRI_ABORTED_BR_BA_RJT	1
475 #define lpfc_wcqe_xa_eo_SHIFT		28
476 #define lpfc_wcqe_xa_eo_MASK		0x00000001
477 #define lpfc_wcqe_xa_eo_WORD		word3
478 #define CQE_XRI_ABORTED_EO_REMOTE	0
479 #define CQE_XRI_ABORTED_EO_LOCAL	1
480 #define lpfc_wcqe_xa_code_SHIFT		lpfc_cqe_code_SHIFT
481 #define lpfc_wcqe_xa_code_MASK		lpfc_cqe_code_MASK
482 #define lpfc_wcqe_xa_code_WORD		lpfc_cqe_code_WORD
483 };
484 
485 /* completion queue entry structure for rqe completion */
486 struct lpfc_rcqe {
487 	uint32_t word0;
488 #define lpfc_rcqe_bindex_SHIFT		16
489 #define lpfc_rcqe_bindex_MASK		0x0000FFF
490 #define lpfc_rcqe_bindex_WORD		word0
491 #define lpfc_rcqe_status_SHIFT		8
492 #define lpfc_rcqe_status_MASK		0x000000FF
493 #define lpfc_rcqe_status_WORD		word0
494 #define FC_STATUS_RQ_SUCCESS		0x10 /* Async receive successful */
495 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 	0x11 /* payload truncated */
496 #define FC_STATUS_INSUFF_BUF_NEED_BUF 	0x12 /* Insufficient buffers */
497 #define FC_STATUS_INSUFF_BUF_FRM_DISC 	0x13 /* Frame Discard */
498 	uint32_t word1;
499 #define lpfc_rcqe_fcf_id_v1_SHIFT	0
500 #define lpfc_rcqe_fcf_id_v1_MASK	0x0000003F
501 #define lpfc_rcqe_fcf_id_v1_WORD	word1
502 	uint32_t word2;
503 #define lpfc_rcqe_length_SHIFT		16
504 #define lpfc_rcqe_length_MASK		0x0000FFFF
505 #define lpfc_rcqe_length_WORD		word2
506 #define lpfc_rcqe_rq_id_SHIFT		6
507 #define lpfc_rcqe_rq_id_MASK		0x000003FF
508 #define lpfc_rcqe_rq_id_WORD		word2
509 #define lpfc_rcqe_fcf_id_SHIFT		0
510 #define lpfc_rcqe_fcf_id_MASK		0x0000003F
511 #define lpfc_rcqe_fcf_id_WORD		word2
512 #define lpfc_rcqe_rq_id_v1_SHIFT	0
513 #define lpfc_rcqe_rq_id_v1_MASK		0x0000FFFF
514 #define lpfc_rcqe_rq_id_v1_WORD		word2
515 	uint32_t word3;
516 #define lpfc_rcqe_valid_SHIFT		lpfc_cqe_valid_SHIFT
517 #define lpfc_rcqe_valid_MASK		lpfc_cqe_valid_MASK
518 #define lpfc_rcqe_valid_WORD		lpfc_cqe_valid_WORD
519 #define lpfc_rcqe_port_SHIFT		30
520 #define lpfc_rcqe_port_MASK		0x00000001
521 #define lpfc_rcqe_port_WORD		word3
522 #define lpfc_rcqe_hdr_length_SHIFT	24
523 #define lpfc_rcqe_hdr_length_MASK	0x0000001F
524 #define lpfc_rcqe_hdr_length_WORD	word3
525 #define lpfc_rcqe_code_SHIFT		lpfc_cqe_code_SHIFT
526 #define lpfc_rcqe_code_MASK		lpfc_cqe_code_MASK
527 #define lpfc_rcqe_code_WORD		lpfc_cqe_code_WORD
528 #define lpfc_rcqe_eof_SHIFT		8
529 #define lpfc_rcqe_eof_MASK		0x000000FF
530 #define lpfc_rcqe_eof_WORD		word3
531 #define FCOE_EOFn	0x41
532 #define FCOE_EOFt	0x42
533 #define FCOE_EOFni	0x49
534 #define FCOE_EOFa	0x50
535 #define lpfc_rcqe_sof_SHIFT		0
536 #define lpfc_rcqe_sof_MASK		0x000000FF
537 #define lpfc_rcqe_sof_WORD		word3
538 #define FCOE_SOFi2	0x2d
539 #define FCOE_SOFi3	0x2e
540 #define FCOE_SOFn2	0x35
541 #define FCOE_SOFn3	0x36
542 };
543 
544 struct lpfc_rqe {
545 	uint32_t address_hi;
546 	uint32_t address_lo;
547 };
548 
549 /* buffer descriptors */
550 struct lpfc_bde4 {
551 	uint32_t addr_hi;
552 	uint32_t addr_lo;
553 	uint32_t word2;
554 #define lpfc_bde4_last_SHIFT		31
555 #define lpfc_bde4_last_MASK		0x00000001
556 #define lpfc_bde4_last_WORD		word2
557 #define lpfc_bde4_sge_offset_SHIFT	0
558 #define lpfc_bde4_sge_offset_MASK	0x000003FF
559 #define lpfc_bde4_sge_offset_WORD	word2
560 	uint32_t word3;
561 #define lpfc_bde4_length_SHIFT		0
562 #define lpfc_bde4_length_MASK		0x000000FF
563 #define lpfc_bde4_length_WORD		word3
564 };
565 
566 struct lpfc_register {
567 	uint32_t word0;
568 };
569 
570 #define LPFC_PORT_SEM_UE_RECOVERABLE    0xE000
571 #define LPFC_PORT_SEM_MASK		0xF000
572 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
573 #define LPFC_UERR_STATUS_HI		0x00A4
574 #define LPFC_UERR_STATUS_LO		0x00A0
575 #define LPFC_UE_MASK_HI			0x00AC
576 #define LPFC_UE_MASK_LO			0x00A8
577 
578 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
579 #define LPFC_SLI_INTF			0x0058
580 #define LPFC_SLI_ASIC_VER		0x009C
581 
582 #define LPFC_CTL_PORT_SEM_OFFSET	0x400
583 #define lpfc_port_smphr_perr_SHIFT	31
584 #define lpfc_port_smphr_perr_MASK	0x1
585 #define lpfc_port_smphr_perr_WORD	word0
586 #define lpfc_port_smphr_sfi_SHIFT	30
587 #define lpfc_port_smphr_sfi_MASK	0x1
588 #define lpfc_port_smphr_sfi_WORD	word0
589 #define lpfc_port_smphr_nip_SHIFT	29
590 #define lpfc_port_smphr_nip_MASK	0x1
591 #define lpfc_port_smphr_nip_WORD	word0
592 #define lpfc_port_smphr_ipc_SHIFT	28
593 #define lpfc_port_smphr_ipc_MASK	0x1
594 #define lpfc_port_smphr_ipc_WORD	word0
595 #define lpfc_port_smphr_scr1_SHIFT	27
596 #define lpfc_port_smphr_scr1_MASK	0x1
597 #define lpfc_port_smphr_scr1_WORD	word0
598 #define lpfc_port_smphr_scr2_SHIFT	26
599 #define lpfc_port_smphr_scr2_MASK	0x1
600 #define lpfc_port_smphr_scr2_WORD	word0
601 #define lpfc_port_smphr_host_scratch_SHIFT	16
602 #define lpfc_port_smphr_host_scratch_MASK	0xFF
603 #define lpfc_port_smphr_host_scratch_WORD	word0
604 #define lpfc_port_smphr_port_status_SHIFT	0
605 #define lpfc_port_smphr_port_status_MASK	0xFFFF
606 #define lpfc_port_smphr_port_status_WORD	word0
607 
608 #define LPFC_POST_STAGE_POWER_ON_RESET			0x0000
609 #define LPFC_POST_STAGE_AWAITING_HOST_RDY		0x0001
610 #define LPFC_POST_STAGE_HOST_RDY			0x0002
611 #define LPFC_POST_STAGE_BE_RESET			0x0003
612 #define LPFC_POST_STAGE_SEEPROM_CS_START		0x0100
613 #define LPFC_POST_STAGE_SEEPROM_CS_DONE			0x0101
614 #define LPFC_POST_STAGE_DDR_CONFIG_START		0x0200
615 #define LPFC_POST_STAGE_DDR_CONFIG_DONE			0x0201
616 #define LPFC_POST_STAGE_DDR_CALIBRATE_START		0x0300
617 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE		0x0301
618 #define LPFC_POST_STAGE_DDR_TEST_START			0x0400
619 #define LPFC_POST_STAGE_DDR_TEST_DONE			0x0401
620 #define LPFC_POST_STAGE_REDBOOT_INIT_START		0x0600
621 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE		0x0601
622 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START		0x0700
623 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE		0x0701
624 #define LPFC_POST_STAGE_ARMFW_START			0x0800
625 #define LPFC_POST_STAGE_DHCP_QUERY_START		0x0900
626 #define LPFC_POST_STAGE_DHCP_QUERY_DONE			0x0901
627 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START	0x0A00
628 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE	0x0A01
629 #define LPFC_POST_STAGE_RC_OPTION_SET			0x0B00
630 #define LPFC_POST_STAGE_SWITCH_LINK			0x0B01
631 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE		0x0B02
632 #define LPFC_POST_STAGE_PERFROM_TFTP			0x0B03
633 #define LPFC_POST_STAGE_PARSE_XML			0x0B04
634 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE			0x0B05
635 #define LPFC_POST_STAGE_FLASH_IMAGE			0x0B06
636 #define LPFC_POST_STAGE_RC_DONE				0x0B07
637 #define LPFC_POST_STAGE_REBOOT_SYSTEM			0x0B08
638 #define LPFC_POST_STAGE_MAC_ADDRESS			0x0C00
639 #define LPFC_POST_STAGE_PORT_READY			0xC000
640 #define LPFC_POST_STAGE_PORT_UE 			0xF000
641 
642 #define LPFC_CTL_PORT_STA_OFFSET	0x404
643 #define lpfc_sliport_status_err_SHIFT	31
644 #define lpfc_sliport_status_err_MASK	0x1
645 #define lpfc_sliport_status_err_WORD	word0
646 #define lpfc_sliport_status_end_SHIFT	30
647 #define lpfc_sliport_status_end_MASK	0x1
648 #define lpfc_sliport_status_end_WORD	word0
649 #define lpfc_sliport_status_oti_SHIFT	29
650 #define lpfc_sliport_status_oti_MASK	0x1
651 #define lpfc_sliport_status_oti_WORD	word0
652 #define lpfc_sliport_status_rn_SHIFT	24
653 #define lpfc_sliport_status_rn_MASK	0x1
654 #define lpfc_sliport_status_rn_WORD	word0
655 #define lpfc_sliport_status_rdy_SHIFT	23
656 #define lpfc_sliport_status_rdy_MASK	0x1
657 #define lpfc_sliport_status_rdy_WORD	word0
658 #define MAX_IF_TYPE_2_RESETS		6
659 
660 #define LPFC_CTL_PORT_CTL_OFFSET	0x408
661 #define lpfc_sliport_ctrl_end_SHIFT	30
662 #define lpfc_sliport_ctrl_end_MASK	0x1
663 #define lpfc_sliport_ctrl_end_WORD	word0
664 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
665 #define LPFC_SLIPORT_BIG_ENDIAN	   1
666 #define lpfc_sliport_ctrl_ip_SHIFT	27
667 #define lpfc_sliport_ctrl_ip_MASK	0x1
668 #define lpfc_sliport_ctrl_ip_WORD	word0
669 #define LPFC_SLIPORT_INIT_PORT	1
670 
671 #define LPFC_CTL_PORT_ER1_OFFSET	0x40C
672 #define LPFC_CTL_PORT_ER2_OFFSET	0x410
673 
674 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET	0x418
675 #define lpfc_sliport_eqdelay_delay_SHIFT 16
676 #define lpfc_sliport_eqdelay_delay_MASK	0xffff
677 #define lpfc_sliport_eqdelay_delay_WORD	word0
678 #define lpfc_sliport_eqdelay_id_SHIFT	0
679 #define lpfc_sliport_eqdelay_id_MASK	0xfff
680 #define lpfc_sliport_eqdelay_id_WORD	word0
681 #define LPFC_SEC_TO_USEC		1000000
682 
683 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
684  * reside in BAR 2.
685  */
686 #define LPFC_SLIPORT_IF0_SMPHR	0x00AC
687 
688 #define LPFC_IMR_MASK_ALL	0xFFFFFFFF
689 #define LPFC_ISCR_CLEAR_ALL	0xFFFFFFFF
690 
691 #define LPFC_HST_ISR0		0x0C18
692 #define LPFC_HST_ISR1		0x0C1C
693 #define LPFC_HST_ISR2		0x0C20
694 #define LPFC_HST_ISR3		0x0C24
695 #define LPFC_HST_ISR4		0x0C28
696 
697 #define LPFC_HST_IMR0		0x0C48
698 #define LPFC_HST_IMR1		0x0C4C
699 #define LPFC_HST_IMR2		0x0C50
700 #define LPFC_HST_IMR3		0x0C54
701 #define LPFC_HST_IMR4		0x0C58
702 
703 #define LPFC_HST_ISCR0		0x0C78
704 #define LPFC_HST_ISCR1		0x0C7C
705 #define LPFC_HST_ISCR2		0x0C80
706 #define LPFC_HST_ISCR3		0x0C84
707 #define LPFC_HST_ISCR4		0x0C88
708 
709 #define LPFC_SLI4_INTR0			BIT0
710 #define LPFC_SLI4_INTR1			BIT1
711 #define LPFC_SLI4_INTR2			BIT2
712 #define LPFC_SLI4_INTR3			BIT3
713 #define LPFC_SLI4_INTR4			BIT4
714 #define LPFC_SLI4_INTR5			BIT5
715 #define LPFC_SLI4_INTR6			BIT6
716 #define LPFC_SLI4_INTR7			BIT7
717 #define LPFC_SLI4_INTR8			BIT8
718 #define LPFC_SLI4_INTR9			BIT9
719 #define LPFC_SLI4_INTR10		BIT10
720 #define LPFC_SLI4_INTR11		BIT11
721 #define LPFC_SLI4_INTR12		BIT12
722 #define LPFC_SLI4_INTR13		BIT13
723 #define LPFC_SLI4_INTR14		BIT14
724 #define LPFC_SLI4_INTR15		BIT15
725 #define LPFC_SLI4_INTR16		BIT16
726 #define LPFC_SLI4_INTR17		BIT17
727 #define LPFC_SLI4_INTR18		BIT18
728 #define LPFC_SLI4_INTR19		BIT19
729 #define LPFC_SLI4_INTR20		BIT20
730 #define LPFC_SLI4_INTR21		BIT21
731 #define LPFC_SLI4_INTR22		BIT22
732 #define LPFC_SLI4_INTR23		BIT23
733 #define LPFC_SLI4_INTR24		BIT24
734 #define LPFC_SLI4_INTR25		BIT25
735 #define LPFC_SLI4_INTR26		BIT26
736 #define LPFC_SLI4_INTR27		BIT27
737 #define LPFC_SLI4_INTR28		BIT28
738 #define LPFC_SLI4_INTR29		BIT29
739 #define LPFC_SLI4_INTR30		BIT30
740 #define LPFC_SLI4_INTR31		BIT31
741 
742 /*
743  * The Doorbell registers defined here exist in different BAR
744  * register sets depending on the UCNA Port's reported if_type
745  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
746  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
747  * BAR0.  For FC ports running SLI4 and if_type 6, they reside in
748  * BAR2. The offsets and base address are different,  so the driver
749  * has to compute the register addresses accordingly
750  */
751 #define LPFC_ULP0_RQ_DOORBELL		0x00A0
752 #define LPFC_ULP1_RQ_DOORBELL		0x00C0
753 #define LPFC_IF6_RQ_DOORBELL		0x0080
754 #define lpfc_rq_db_list_fm_num_posted_SHIFT	24
755 #define lpfc_rq_db_list_fm_num_posted_MASK	0x00FF
756 #define lpfc_rq_db_list_fm_num_posted_WORD	word0
757 #define lpfc_rq_db_list_fm_index_SHIFT		16
758 #define lpfc_rq_db_list_fm_index_MASK		0x00FF
759 #define lpfc_rq_db_list_fm_index_WORD		word0
760 #define lpfc_rq_db_list_fm_id_SHIFT		0
761 #define lpfc_rq_db_list_fm_id_MASK		0xFFFF
762 #define lpfc_rq_db_list_fm_id_WORD		word0
763 #define lpfc_rq_db_ring_fm_num_posted_SHIFT	16
764 #define lpfc_rq_db_ring_fm_num_posted_MASK	0x3FFF
765 #define lpfc_rq_db_ring_fm_num_posted_WORD	word0
766 #define lpfc_rq_db_ring_fm_id_SHIFT		0
767 #define lpfc_rq_db_ring_fm_id_MASK		0xFFFF
768 #define lpfc_rq_db_ring_fm_id_WORD		word0
769 
770 #define LPFC_ULP0_WQ_DOORBELL		0x0040
771 #define LPFC_ULP1_WQ_DOORBELL		0x0060
772 #define lpfc_wq_db_list_fm_num_posted_SHIFT	24
773 #define lpfc_wq_db_list_fm_num_posted_MASK	0x00FF
774 #define lpfc_wq_db_list_fm_num_posted_WORD	word0
775 #define lpfc_wq_db_list_fm_index_SHIFT		16
776 #define lpfc_wq_db_list_fm_index_MASK		0x00FF
777 #define lpfc_wq_db_list_fm_index_WORD		word0
778 #define lpfc_wq_db_list_fm_id_SHIFT		0
779 #define lpfc_wq_db_list_fm_id_MASK		0xFFFF
780 #define lpfc_wq_db_list_fm_id_WORD		word0
781 #define lpfc_wq_db_ring_fm_num_posted_SHIFT     16
782 #define lpfc_wq_db_ring_fm_num_posted_MASK      0x3FFF
783 #define lpfc_wq_db_ring_fm_num_posted_WORD      word0
784 #define lpfc_wq_db_ring_fm_id_SHIFT             0
785 #define lpfc_wq_db_ring_fm_id_MASK              0xFFFF
786 #define lpfc_wq_db_ring_fm_id_WORD              word0
787 
788 #define LPFC_IF6_WQ_DOORBELL		0x0040
789 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT	24
790 #define lpfc_if6_wq_db_list_fm_num_posted_MASK	0x00FF
791 #define lpfc_if6_wq_db_list_fm_num_posted_WORD	word0
792 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT	23
793 #define lpfc_if6_wq_db_list_fm_dpp_MASK		0x0001
794 #define lpfc_if6_wq_db_list_fm_dpp_WORD		word0
795 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT	16
796 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK	0x001F
797 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD	word0
798 #define lpfc_if6_wq_db_list_fm_id_SHIFT		0
799 #define lpfc_if6_wq_db_list_fm_id_MASK		0xFFFF
800 #define lpfc_if6_wq_db_list_fm_id_WORD		word0
801 
802 #define LPFC_EQCQ_DOORBELL		0x0120
803 #define lpfc_eqcq_doorbell_se_SHIFT		31
804 #define lpfc_eqcq_doorbell_se_MASK		0x0001
805 #define lpfc_eqcq_doorbell_se_WORD		word0
806 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF	0
807 #define LPFC_EQCQ_SOLICIT_ENABLE_ON	1
808 #define lpfc_eqcq_doorbell_arm_SHIFT		29
809 #define lpfc_eqcq_doorbell_arm_MASK		0x0001
810 #define lpfc_eqcq_doorbell_arm_WORD		word0
811 #define lpfc_eqcq_doorbell_num_released_SHIFT	16
812 #define lpfc_eqcq_doorbell_num_released_MASK	0x1FFF
813 #define lpfc_eqcq_doorbell_num_released_WORD	word0
814 #define lpfc_eqcq_doorbell_qt_SHIFT		10
815 #define lpfc_eqcq_doorbell_qt_MASK		0x0001
816 #define lpfc_eqcq_doorbell_qt_WORD		word0
817 #define LPFC_QUEUE_TYPE_COMPLETION	0
818 #define LPFC_QUEUE_TYPE_EVENT		1
819 #define lpfc_eqcq_doorbell_eqci_SHIFT		9
820 #define lpfc_eqcq_doorbell_eqci_MASK		0x0001
821 #define lpfc_eqcq_doorbell_eqci_WORD		word0
822 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT	0
823 #define lpfc_eqcq_doorbell_cqid_lo_MASK		0x03FF
824 #define lpfc_eqcq_doorbell_cqid_lo_WORD		word0
825 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT	11
826 #define lpfc_eqcq_doorbell_cqid_hi_MASK		0x001F
827 #define lpfc_eqcq_doorbell_cqid_hi_WORD		word0
828 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT	0
829 #define lpfc_eqcq_doorbell_eqid_lo_MASK		0x01FF
830 #define lpfc_eqcq_doorbell_eqid_lo_WORD		word0
831 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT	11
832 #define lpfc_eqcq_doorbell_eqid_hi_MASK		0x001F
833 #define lpfc_eqcq_doorbell_eqid_hi_WORD		word0
834 #define LPFC_CQID_HI_FIELD_SHIFT		10
835 #define LPFC_EQID_HI_FIELD_SHIFT		9
836 
837 #define LPFC_IF6_CQ_DOORBELL			0x00C0
838 #define lpfc_if6_cq_doorbell_se_SHIFT		31
839 #define lpfc_if6_cq_doorbell_se_MASK		0x0001
840 #define lpfc_if6_cq_doorbell_se_WORD		word0
841 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF		0
842 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON		1
843 #define lpfc_if6_cq_doorbell_arm_SHIFT		29
844 #define lpfc_if6_cq_doorbell_arm_MASK		0x0001
845 #define lpfc_if6_cq_doorbell_arm_WORD		word0
846 #define lpfc_if6_cq_doorbell_num_released_SHIFT	16
847 #define lpfc_if6_cq_doorbell_num_released_MASK	0x1FFF
848 #define lpfc_if6_cq_doorbell_num_released_WORD	word0
849 #define lpfc_if6_cq_doorbell_cqid_SHIFT		0
850 #define lpfc_if6_cq_doorbell_cqid_MASK		0xFFFF
851 #define lpfc_if6_cq_doorbell_cqid_WORD		word0
852 
853 #define LPFC_IF6_EQ_DOORBELL			0x0120
854 #define lpfc_if6_eq_doorbell_io_SHIFT		31
855 #define lpfc_if6_eq_doorbell_io_MASK		0x0001
856 #define lpfc_if6_eq_doorbell_io_WORD		word0
857 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF		0
858 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON		1
859 #define lpfc_if6_eq_doorbell_arm_SHIFT		29
860 #define lpfc_if6_eq_doorbell_arm_MASK		0x0001
861 #define lpfc_if6_eq_doorbell_arm_WORD		word0
862 #define lpfc_if6_eq_doorbell_num_released_SHIFT	16
863 #define lpfc_if6_eq_doorbell_num_released_MASK	0x1FFF
864 #define lpfc_if6_eq_doorbell_num_released_WORD	word0
865 #define lpfc_if6_eq_doorbell_eqid_SHIFT		0
866 #define lpfc_if6_eq_doorbell_eqid_MASK		0x0FFF
867 #define lpfc_if6_eq_doorbell_eqid_WORD		word0
868 
869 #define LPFC_BMBX			0x0160
870 #define lpfc_bmbx_addr_SHIFT		2
871 #define lpfc_bmbx_addr_MASK		0x3FFFFFFF
872 #define lpfc_bmbx_addr_WORD		word0
873 #define lpfc_bmbx_hi_SHIFT		1
874 #define lpfc_bmbx_hi_MASK		0x0001
875 #define lpfc_bmbx_hi_WORD		word0
876 #define lpfc_bmbx_rdy_SHIFT		0
877 #define lpfc_bmbx_rdy_MASK		0x0001
878 #define lpfc_bmbx_rdy_WORD		word0
879 
880 #define LPFC_MQ_DOORBELL			0x0140
881 #define LPFC_IF6_MQ_DOORBELL			0x0160
882 #define lpfc_mq_doorbell_num_posted_SHIFT	16
883 #define lpfc_mq_doorbell_num_posted_MASK	0x3FFF
884 #define lpfc_mq_doorbell_num_posted_WORD	word0
885 #define lpfc_mq_doorbell_id_SHIFT		0
886 #define lpfc_mq_doorbell_id_MASK		0xFFFF
887 #define lpfc_mq_doorbell_id_WORD		word0
888 
889 struct lpfc_sli4_cfg_mhdr {
890 	uint32_t word1;
891 #define lpfc_mbox_hdr_emb_SHIFT		0
892 #define lpfc_mbox_hdr_emb_MASK		0x00000001
893 #define lpfc_mbox_hdr_emb_WORD		word1
894 #define lpfc_mbox_hdr_sge_cnt_SHIFT	3
895 #define lpfc_mbox_hdr_sge_cnt_MASK	0x0000001F
896 #define lpfc_mbox_hdr_sge_cnt_WORD	word1
897 	uint32_t payload_length;
898 	uint32_t tag_lo;
899 	uint32_t tag_hi;
900 	uint32_t reserved5;
901 };
902 
903 union lpfc_sli4_cfg_shdr {
904 	struct {
905 		uint32_t word6;
906 #define lpfc_mbox_hdr_opcode_SHIFT	0
907 #define lpfc_mbox_hdr_opcode_MASK	0x000000FF
908 #define lpfc_mbox_hdr_opcode_WORD	word6
909 #define lpfc_mbox_hdr_subsystem_SHIFT	8
910 #define lpfc_mbox_hdr_subsystem_MASK	0x000000FF
911 #define lpfc_mbox_hdr_subsystem_WORD	word6
912 #define lpfc_mbox_hdr_port_number_SHIFT	16
913 #define lpfc_mbox_hdr_port_number_MASK	0x000000FF
914 #define lpfc_mbox_hdr_port_number_WORD	word6
915 #define lpfc_mbox_hdr_domain_SHIFT	24
916 #define lpfc_mbox_hdr_domain_MASK	0x000000FF
917 #define lpfc_mbox_hdr_domain_WORD	word6
918 		uint32_t timeout;
919 		uint32_t request_length;
920 		uint32_t word9;
921 #define lpfc_mbox_hdr_version_SHIFT	0
922 #define lpfc_mbox_hdr_version_MASK	0x000000FF
923 #define lpfc_mbox_hdr_version_WORD	word9
924 #define lpfc_mbox_hdr_pf_num_SHIFT	16
925 #define lpfc_mbox_hdr_pf_num_MASK	0x000000FF
926 #define lpfc_mbox_hdr_pf_num_WORD	word9
927 #define lpfc_mbox_hdr_vh_num_SHIFT	24
928 #define lpfc_mbox_hdr_vh_num_MASK	0x000000FF
929 #define lpfc_mbox_hdr_vh_num_WORD	word9
930 #define LPFC_Q_CREATE_VERSION_2	2
931 #define LPFC_Q_CREATE_VERSION_1	1
932 #define LPFC_Q_CREATE_VERSION_0	0
933 #define LPFC_OPCODE_VERSION_0	0
934 #define LPFC_OPCODE_VERSION_1	1
935 	} request;
936 	struct {
937 		uint32_t word6;
938 #define lpfc_mbox_hdr_opcode_SHIFT		0
939 #define lpfc_mbox_hdr_opcode_MASK		0x000000FF
940 #define lpfc_mbox_hdr_opcode_WORD		word6
941 #define lpfc_mbox_hdr_subsystem_SHIFT		8
942 #define lpfc_mbox_hdr_subsystem_MASK		0x000000FF
943 #define lpfc_mbox_hdr_subsystem_WORD		word6
944 #define lpfc_mbox_hdr_domain_SHIFT		24
945 #define lpfc_mbox_hdr_domain_MASK		0x000000FF
946 #define lpfc_mbox_hdr_domain_WORD		word6
947 		uint32_t word7;
948 #define lpfc_mbox_hdr_status_SHIFT		0
949 #define lpfc_mbox_hdr_status_MASK		0x000000FF
950 #define lpfc_mbox_hdr_status_WORD		word7
951 #define lpfc_mbox_hdr_add_status_SHIFT		8
952 #define lpfc_mbox_hdr_add_status_MASK		0x000000FF
953 #define lpfc_mbox_hdr_add_status_WORD		word7
954 		uint32_t response_length;
955 		uint32_t actual_response_length;
956 	} response;
957 };
958 
959 /* Mailbox Header structures.
960  * struct mbox_header is defined for first generation SLI4_CFG mailbox
961  * calls deployed for BE-based ports.
962  *
963  * struct sli4_mbox_header is defined for second generation SLI4
964  * ports that don't deploy the SLI4_CFG mechanism.
965  */
966 struct mbox_header {
967 	struct lpfc_sli4_cfg_mhdr cfg_mhdr;
968 	union  lpfc_sli4_cfg_shdr cfg_shdr;
969 };
970 
971 #define LPFC_EXTENT_LOCAL		0
972 #define LPFC_TIMEOUT_DEFAULT		0
973 #define LPFC_EXTENT_VERSION_DEFAULT	0
974 
975 /* Subsystem Definitions */
976 #define LPFC_MBOX_SUBSYSTEM_NA		0x0
977 #define LPFC_MBOX_SUBSYSTEM_COMMON	0x1
978 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL	0xB
979 #define LPFC_MBOX_SUBSYSTEM_FCOE	0xC
980 
981 /* Device Specific Definitions */
982 
983 /* The HOST ENDIAN defines are in Big Endian format. */
984 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
985 #define HOST_ENDIAN_HIGH_WORD1	0xFF7856FF
986 
987 /* Common Opcodes */
988 #define LPFC_MBOX_OPCODE_NA				0x00
989 #define LPFC_MBOX_OPCODE_CQ_CREATE			0x0C
990 #define LPFC_MBOX_OPCODE_EQ_CREATE			0x0D
991 #define LPFC_MBOX_OPCODE_MQ_CREATE			0x15
992 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES		0x20
993 #define LPFC_MBOX_OPCODE_NOP				0x21
994 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY		0x29
995 #define LPFC_MBOX_OPCODE_MQ_DESTROY			0x35
996 #define LPFC_MBOX_OPCODE_CQ_DESTROY			0x36
997 #define LPFC_MBOX_OPCODE_EQ_DESTROY			0x37
998 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG			0x3A
999 #define LPFC_MBOX_OPCODE_FUNCTION_RESET			0x3D
1000 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG	0x3E
1001 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG		0x43
1002 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG              0x45
1003 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG              0x46
1004 #define LPFC_MBOX_OPCODE_GET_PORT_NAME			0x4D
1005 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT			0x5A
1006 #define LPFC_MBOX_OPCODE_GET_VPD_DATA			0x5B
1007 #define LPFC_MBOX_OPCODE_SET_HOST_DATA			0x5D
1008 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION		0x73
1009 #define LPFC_MBOX_OPCODE_RESET_LICENSES			0x74
1010 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO		0x9A
1011 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT		0x9B
1012 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT		0x9C
1013 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT		0x9D
1014 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG		0xA0
1015 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES		0xA1
1016 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG		0xA4
1017 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG		0xA5
1018 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST		0xA6
1019 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE		0xA8
1020 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG	0xA9
1021 #define LPFC_MBOX_OPCODE_READ_OBJECT			0xAB
1022 #define LPFC_MBOX_OPCODE_WRITE_OBJECT			0xAC
1023 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST		0xAD
1024 #define LPFC_MBOX_OPCODE_DELETE_OBJECT			0xAE
1025 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS		0xB5
1026 #define LPFC_MBOX_OPCODE_SET_FEATURES                   0xBF
1027 
1028 /* FCoE Opcodes */
1029 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE			0x01
1030 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY		0x02
1031 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES		0x03
1032 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES		0x04
1033 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE			0x05
1034 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY		0x06
1035 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE		0x08
1036 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF			0x09
1037 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF		0x0A
1038 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE		0x0B
1039 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF		0x10
1040 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET		0x1D
1041 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS	0x21
1042 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE		0x22
1043 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK	0x23
1044 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE		0x42
1045 
1046 /* Low level Opcodes */
1047 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION		0x37
1048 
1049 /* Mailbox command structures */
1050 struct eq_context {
1051 	uint32_t word0;
1052 #define lpfc_eq_context_size_SHIFT	31
1053 #define lpfc_eq_context_size_MASK	0x00000001
1054 #define lpfc_eq_context_size_WORD	word0
1055 #define LPFC_EQE_SIZE_4			0x0
1056 #define LPFC_EQE_SIZE_16		0x1
1057 #define lpfc_eq_context_valid_SHIFT	29
1058 #define lpfc_eq_context_valid_MASK	0x00000001
1059 #define lpfc_eq_context_valid_WORD	word0
1060 #define lpfc_eq_context_autovalid_SHIFT 28
1061 #define lpfc_eq_context_autovalid_MASK  0x00000001
1062 #define lpfc_eq_context_autovalid_WORD  word0
1063 	uint32_t word1;
1064 #define lpfc_eq_context_count_SHIFT	26
1065 #define lpfc_eq_context_count_MASK	0x00000003
1066 #define lpfc_eq_context_count_WORD	word1
1067 #define LPFC_EQ_CNT_256		0x0
1068 #define LPFC_EQ_CNT_512		0x1
1069 #define LPFC_EQ_CNT_1024	0x2
1070 #define LPFC_EQ_CNT_2048	0x3
1071 #define LPFC_EQ_CNT_4096	0x4
1072 	uint32_t word2;
1073 #define lpfc_eq_context_delay_multi_SHIFT	13
1074 #define lpfc_eq_context_delay_multi_MASK	0x000003FF
1075 #define lpfc_eq_context_delay_multi_WORD	word2
1076 	uint32_t reserved3;
1077 };
1078 
1079 struct eq_delay_info {
1080 	uint32_t eq_id;
1081 	uint32_t phase;
1082 	uint32_t delay_multi;
1083 };
1084 #define	LPFC_MAX_EQ_DELAY_EQID_CNT	8
1085 
1086 struct sgl_page_pairs {
1087 	uint32_t sgl_pg0_addr_lo;
1088 	uint32_t sgl_pg0_addr_hi;
1089 	uint32_t sgl_pg1_addr_lo;
1090 	uint32_t sgl_pg1_addr_hi;
1091 };
1092 
1093 struct lpfc_mbx_post_sgl_pages {
1094 	struct mbox_header header;
1095 	uint32_t word0;
1096 #define lpfc_post_sgl_pages_xri_SHIFT	0
1097 #define lpfc_post_sgl_pages_xri_MASK	0x0000FFFF
1098 #define lpfc_post_sgl_pages_xri_WORD	word0
1099 #define lpfc_post_sgl_pages_xricnt_SHIFT	16
1100 #define lpfc_post_sgl_pages_xricnt_MASK	0x0000FFFF
1101 #define lpfc_post_sgl_pages_xricnt_WORD	word0
1102 	struct sgl_page_pairs  sgl_pg_pairs[1];
1103 };
1104 
1105 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1106 struct lpfc_mbx_post_uembed_sgl_page1 {
1107 	union  lpfc_sli4_cfg_shdr cfg_shdr;
1108 	uint32_t word0;
1109 	struct sgl_page_pairs sgl_pg_pairs;
1110 };
1111 
1112 struct lpfc_mbx_sge {
1113 	uint32_t pa_lo;
1114 	uint32_t pa_hi;
1115 	uint32_t length;
1116 };
1117 
1118 struct lpfc_mbx_nembed_cmd {
1119 	struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1120 #define LPFC_SLI4_MBX_SGE_MAX_PAGES	19
1121 	struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1122 };
1123 
1124 struct lpfc_mbx_nembed_sge_virt {
1125 	void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1126 };
1127 
1128 struct lpfc_mbx_eq_create {
1129 	struct mbox_header header;
1130 	union {
1131 		struct {
1132 			uint32_t word0;
1133 #define lpfc_mbx_eq_create_num_pages_SHIFT	0
1134 #define lpfc_mbx_eq_create_num_pages_MASK	0x0000FFFF
1135 #define lpfc_mbx_eq_create_num_pages_WORD	word0
1136 			struct eq_context context;
1137 			struct dma_address page[LPFC_MAX_EQ_PAGE];
1138 		} request;
1139 		struct {
1140 			uint32_t word0;
1141 #define lpfc_mbx_eq_create_q_id_SHIFT	0
1142 #define lpfc_mbx_eq_create_q_id_MASK	0x0000FFFF
1143 #define lpfc_mbx_eq_create_q_id_WORD	word0
1144 		} response;
1145 	} u;
1146 };
1147 
1148 struct lpfc_mbx_modify_eq_delay {
1149 	struct mbox_header header;
1150 	union {
1151 		struct {
1152 			uint32_t num_eq;
1153 			struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1154 		} request;
1155 		struct {
1156 			uint32_t word0;
1157 		} response;
1158 	} u;
1159 };
1160 
1161 struct lpfc_mbx_eq_destroy {
1162 	struct mbox_header header;
1163 	union {
1164 		struct {
1165 			uint32_t word0;
1166 #define lpfc_mbx_eq_destroy_q_id_SHIFT	0
1167 #define lpfc_mbx_eq_destroy_q_id_MASK	0x0000FFFF
1168 #define lpfc_mbx_eq_destroy_q_id_WORD	word0
1169 		} request;
1170 		struct {
1171 			uint32_t word0;
1172 		} response;
1173 	} u;
1174 };
1175 
1176 struct lpfc_mbx_nop {
1177 	struct mbox_header header;
1178 	uint32_t context[2];
1179 };
1180 
1181 
1182 
1183 struct lpfc_mbx_set_ras_fwlog {
1184 	struct mbox_header header;
1185 	union {
1186 		struct {
1187 			uint32_t word4;
1188 #define lpfc_fwlog_enable_SHIFT		0
1189 #define lpfc_fwlog_enable_MASK		0x00000001
1190 #define lpfc_fwlog_enable_WORD		word4
1191 #define lpfc_fwlog_loglvl_SHIFT		8
1192 #define lpfc_fwlog_loglvl_MASK		0x0000000F
1193 #define lpfc_fwlog_loglvl_WORD		word4
1194 #define lpfc_fwlog_ra_SHIFT		15
1195 #define lpfc_fwlog_ra_WORD		0x00000008
1196 #define lpfc_fwlog_buffcnt_SHIFT	16
1197 #define lpfc_fwlog_buffcnt_MASK		0x000000FF
1198 #define lpfc_fwlog_buffcnt_WORD		word4
1199 #define lpfc_fwlog_buffsz_SHIFT		24
1200 #define lpfc_fwlog_buffsz_MASK		0x000000FF
1201 #define lpfc_fwlog_buffsz_WORD		word4
1202 			uint32_t word5;
1203 #define lpfc_fwlog_acqe_SHIFT		0
1204 #define lpfc_fwlog_acqe_MASK		0x0000FFFF
1205 #define lpfc_fwlog_acqe_WORD		word5
1206 #define lpfc_fwlog_cqid_SHIFT		16
1207 #define lpfc_fwlog_cqid_MASK		0x0000FFFF
1208 #define lpfc_fwlog_cqid_WORD		word5
1209 #define LPFC_MAX_FWLOG_PAGE	16
1210 			struct dma_address lwpd;
1211 			struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE];
1212 		} request;
1213 		struct {
1214 			uint32_t word0;
1215 		} response;
1216 	} u;
1217 };
1218 
1219 
1220 struct cq_context {
1221 	uint32_t word0;
1222 #define lpfc_cq_context_event_SHIFT	31
1223 #define lpfc_cq_context_event_MASK	0x00000001
1224 #define lpfc_cq_context_event_WORD	word0
1225 #define lpfc_cq_context_valid_SHIFT	29
1226 #define lpfc_cq_context_valid_MASK	0x00000001
1227 #define lpfc_cq_context_valid_WORD	word0
1228 #define lpfc_cq_context_count_SHIFT	27
1229 #define lpfc_cq_context_count_MASK	0x00000003
1230 #define lpfc_cq_context_count_WORD	word0
1231 #define LPFC_CQ_CNT_256		0x0
1232 #define LPFC_CQ_CNT_512		0x1
1233 #define LPFC_CQ_CNT_1024	0x2
1234 #define LPFC_CQ_CNT_WORD7	0x3
1235 #define lpfc_cq_context_autovalid_SHIFT 15
1236 #define lpfc_cq_context_autovalid_MASK  0x00000001
1237 #define lpfc_cq_context_autovalid_WORD  word0
1238 	uint32_t word1;
1239 #define lpfc_cq_eq_id_SHIFT		22	/* Version 0 Only */
1240 #define lpfc_cq_eq_id_MASK		0x000000FF
1241 #define lpfc_cq_eq_id_WORD		word1
1242 #define lpfc_cq_eq_id_2_SHIFT		0 	/* Version 2 Only */
1243 #define lpfc_cq_eq_id_2_MASK		0x0000FFFF
1244 #define lpfc_cq_eq_id_2_WORD		word1
1245 	uint32_t lpfc_cq_context_count;		/* Version 2 Only */
1246 	uint32_t reserved1;
1247 };
1248 
1249 struct lpfc_mbx_cq_create {
1250 	struct mbox_header header;
1251 	union {
1252 		struct {
1253 			uint32_t word0;
1254 #define lpfc_mbx_cq_create_page_size_SHIFT	16	/* Version 2 Only */
1255 #define lpfc_mbx_cq_create_page_size_MASK	0x000000FF
1256 #define lpfc_mbx_cq_create_page_size_WORD	word0
1257 #define lpfc_mbx_cq_create_num_pages_SHIFT	0
1258 #define lpfc_mbx_cq_create_num_pages_MASK	0x0000FFFF
1259 #define lpfc_mbx_cq_create_num_pages_WORD	word0
1260 			struct cq_context context;
1261 			struct dma_address page[LPFC_MAX_CQ_PAGE];
1262 		} request;
1263 		struct {
1264 			uint32_t word0;
1265 #define lpfc_mbx_cq_create_q_id_SHIFT	0
1266 #define lpfc_mbx_cq_create_q_id_MASK	0x0000FFFF
1267 #define lpfc_mbx_cq_create_q_id_WORD	word0
1268 		} response;
1269 	} u;
1270 };
1271 
1272 struct lpfc_mbx_cq_create_set {
1273 	union  lpfc_sli4_cfg_shdr cfg_shdr;
1274 	union {
1275 		struct {
1276 			uint32_t word0;
1277 #define lpfc_mbx_cq_create_set_page_size_SHIFT	16	/* Version 2 Only */
1278 #define lpfc_mbx_cq_create_set_page_size_MASK	0x000000FF
1279 #define lpfc_mbx_cq_create_set_page_size_WORD	word0
1280 #define lpfc_mbx_cq_create_set_num_pages_SHIFT	0
1281 #define lpfc_mbx_cq_create_set_num_pages_MASK	0x0000FFFF
1282 #define lpfc_mbx_cq_create_set_num_pages_WORD	word0
1283 			uint32_t word1;
1284 #define lpfc_mbx_cq_create_set_evt_SHIFT	31
1285 #define lpfc_mbx_cq_create_set_evt_MASK		0x00000001
1286 #define lpfc_mbx_cq_create_set_evt_WORD		word1
1287 #define lpfc_mbx_cq_create_set_valid_SHIFT	29
1288 #define lpfc_mbx_cq_create_set_valid_MASK	0x00000001
1289 #define lpfc_mbx_cq_create_set_valid_WORD	word1
1290 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT	27
1291 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK	0x00000003
1292 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD	word1
1293 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT	25
1294 #define lpfc_mbx_cq_create_set_cqe_size_MASK	0x00000003
1295 #define lpfc_mbx_cq_create_set_cqe_size_WORD	word1
1296 #define lpfc_mbx_cq_create_set_autovalid_SHIFT	15
1297 #define lpfc_mbx_cq_create_set_autovalid_MASK	0x0000001
1298 #define lpfc_mbx_cq_create_set_autovalid_WORD	word1
1299 #define lpfc_mbx_cq_create_set_nodelay_SHIFT	14
1300 #define lpfc_mbx_cq_create_set_nodelay_MASK	0x00000001
1301 #define lpfc_mbx_cq_create_set_nodelay_WORD	word1
1302 #define lpfc_mbx_cq_create_set_clswm_SHIFT	12
1303 #define lpfc_mbx_cq_create_set_clswm_MASK	0x00000003
1304 #define lpfc_mbx_cq_create_set_clswm_WORD	word1
1305 			uint32_t word2;
1306 #define lpfc_mbx_cq_create_set_arm_SHIFT	31
1307 #define lpfc_mbx_cq_create_set_arm_MASK		0x00000001
1308 #define lpfc_mbx_cq_create_set_arm_WORD		word2
1309 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT	16
1310 #define lpfc_mbx_cq_create_set_cq_cnt_MASK	0x00007FFF
1311 #define lpfc_mbx_cq_create_set_cq_cnt_WORD	word2
1312 #define lpfc_mbx_cq_create_set_num_cq_SHIFT	0
1313 #define lpfc_mbx_cq_create_set_num_cq_MASK	0x0000FFFF
1314 #define lpfc_mbx_cq_create_set_num_cq_WORD	word2
1315 			uint32_t word3;
1316 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT	16
1317 #define lpfc_mbx_cq_create_set_eq_id1_MASK	0x0000FFFF
1318 #define lpfc_mbx_cq_create_set_eq_id1_WORD	word3
1319 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT	0
1320 #define lpfc_mbx_cq_create_set_eq_id0_MASK	0x0000FFFF
1321 #define lpfc_mbx_cq_create_set_eq_id0_WORD	word3
1322 			uint32_t word4;
1323 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT	16
1324 #define lpfc_mbx_cq_create_set_eq_id3_MASK	0x0000FFFF
1325 #define lpfc_mbx_cq_create_set_eq_id3_WORD	word4
1326 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT	0
1327 #define lpfc_mbx_cq_create_set_eq_id2_MASK	0x0000FFFF
1328 #define lpfc_mbx_cq_create_set_eq_id2_WORD	word4
1329 			uint32_t word5;
1330 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT	16
1331 #define lpfc_mbx_cq_create_set_eq_id5_MASK	0x0000FFFF
1332 #define lpfc_mbx_cq_create_set_eq_id5_WORD	word5
1333 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT	0
1334 #define lpfc_mbx_cq_create_set_eq_id4_MASK	0x0000FFFF
1335 #define lpfc_mbx_cq_create_set_eq_id4_WORD	word5
1336 			uint32_t word6;
1337 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT	16
1338 #define lpfc_mbx_cq_create_set_eq_id7_MASK	0x0000FFFF
1339 #define lpfc_mbx_cq_create_set_eq_id7_WORD	word6
1340 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT	0
1341 #define lpfc_mbx_cq_create_set_eq_id6_MASK	0x0000FFFF
1342 #define lpfc_mbx_cq_create_set_eq_id6_WORD	word6
1343 			uint32_t word7;
1344 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT	16
1345 #define lpfc_mbx_cq_create_set_eq_id9_MASK	0x0000FFFF
1346 #define lpfc_mbx_cq_create_set_eq_id9_WORD	word7
1347 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT	0
1348 #define lpfc_mbx_cq_create_set_eq_id8_MASK	0x0000FFFF
1349 #define lpfc_mbx_cq_create_set_eq_id8_WORD	word7
1350 			uint32_t word8;
1351 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT	16
1352 #define lpfc_mbx_cq_create_set_eq_id11_MASK	0x0000FFFF
1353 #define lpfc_mbx_cq_create_set_eq_id11_WORD	word8
1354 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT	0
1355 #define lpfc_mbx_cq_create_set_eq_id10_MASK	0x0000FFFF
1356 #define lpfc_mbx_cq_create_set_eq_id10_WORD	word8
1357 			uint32_t word9;
1358 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT	16
1359 #define lpfc_mbx_cq_create_set_eq_id13_MASK	0x0000FFFF
1360 #define lpfc_mbx_cq_create_set_eq_id13_WORD	word9
1361 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT	0
1362 #define lpfc_mbx_cq_create_set_eq_id12_MASK	0x0000FFFF
1363 #define lpfc_mbx_cq_create_set_eq_id12_WORD	word9
1364 			uint32_t word10;
1365 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT	16
1366 #define lpfc_mbx_cq_create_set_eq_id15_MASK	0x0000FFFF
1367 #define lpfc_mbx_cq_create_set_eq_id15_WORD	word10
1368 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT	0
1369 #define lpfc_mbx_cq_create_set_eq_id14_MASK	0x0000FFFF
1370 #define lpfc_mbx_cq_create_set_eq_id14_WORD	word10
1371 			struct dma_address page[1];
1372 		} request;
1373 		struct {
1374 			uint32_t word0;
1375 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT	16
1376 #define lpfc_mbx_cq_create_set_num_alloc_MASK	0x0000FFFF
1377 #define lpfc_mbx_cq_create_set_num_alloc_WORD	word0
1378 #define lpfc_mbx_cq_create_set_base_id_SHIFT	0
1379 #define lpfc_mbx_cq_create_set_base_id_MASK	0x0000FFFF
1380 #define lpfc_mbx_cq_create_set_base_id_WORD	word0
1381 		} response;
1382 	} u;
1383 };
1384 
1385 struct lpfc_mbx_cq_destroy {
1386 	struct mbox_header header;
1387 	union {
1388 		struct {
1389 			uint32_t word0;
1390 #define lpfc_mbx_cq_destroy_q_id_SHIFT	0
1391 #define lpfc_mbx_cq_destroy_q_id_MASK	0x0000FFFF
1392 #define lpfc_mbx_cq_destroy_q_id_WORD	word0
1393 		} request;
1394 		struct {
1395 			uint32_t word0;
1396 		} response;
1397 	} u;
1398 };
1399 
1400 struct wq_context {
1401 	uint32_t reserved0;
1402 	uint32_t reserved1;
1403 	uint32_t reserved2;
1404 	uint32_t reserved3;
1405 };
1406 
1407 struct lpfc_mbx_wq_create {
1408 	struct mbox_header header;
1409 	union {
1410 		struct {	/* Version 0 Request */
1411 			uint32_t word0;
1412 #define lpfc_mbx_wq_create_num_pages_SHIFT	0
1413 #define lpfc_mbx_wq_create_num_pages_MASK	0x000000FF
1414 #define lpfc_mbx_wq_create_num_pages_WORD	word0
1415 #define lpfc_mbx_wq_create_dua_SHIFT		8
1416 #define lpfc_mbx_wq_create_dua_MASK		0x00000001
1417 #define lpfc_mbx_wq_create_dua_WORD		word0
1418 #define lpfc_mbx_wq_create_cq_id_SHIFT		16
1419 #define lpfc_mbx_wq_create_cq_id_MASK		0x0000FFFF
1420 #define lpfc_mbx_wq_create_cq_id_WORD		word0
1421 			struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1422 			uint32_t word9;
1423 #define lpfc_mbx_wq_create_bua_SHIFT		0
1424 #define lpfc_mbx_wq_create_bua_MASK		0x00000001
1425 #define lpfc_mbx_wq_create_bua_WORD		word9
1426 #define lpfc_mbx_wq_create_ulp_num_SHIFT	8
1427 #define lpfc_mbx_wq_create_ulp_num_MASK		0x000000FF
1428 #define lpfc_mbx_wq_create_ulp_num_WORD		word9
1429 		} request;
1430 		struct {	/* Version 1 Request */
1431 			uint32_t word0;	/* Word 0 is the same as in v0 */
1432 			uint32_t word1;
1433 #define lpfc_mbx_wq_create_page_size_SHIFT	0
1434 #define lpfc_mbx_wq_create_page_size_MASK	0x000000FF
1435 #define lpfc_mbx_wq_create_page_size_WORD	word1
1436 #define LPFC_WQ_PAGE_SIZE_4096	0x1
1437 #define lpfc_mbx_wq_create_dpp_req_SHIFT	15
1438 #define lpfc_mbx_wq_create_dpp_req_MASK		0x00000001
1439 #define lpfc_mbx_wq_create_dpp_req_WORD		word1
1440 #define lpfc_mbx_wq_create_doe_SHIFT		14
1441 #define lpfc_mbx_wq_create_doe_MASK		0x00000001
1442 #define lpfc_mbx_wq_create_doe_WORD		word1
1443 #define lpfc_mbx_wq_create_toe_SHIFT		13
1444 #define lpfc_mbx_wq_create_toe_MASK		0x00000001
1445 #define lpfc_mbx_wq_create_toe_WORD		word1
1446 #define lpfc_mbx_wq_create_wqe_size_SHIFT	8
1447 #define lpfc_mbx_wq_create_wqe_size_MASK	0x0000000F
1448 #define lpfc_mbx_wq_create_wqe_size_WORD	word1
1449 #define LPFC_WQ_WQE_SIZE_64	0x5
1450 #define LPFC_WQ_WQE_SIZE_128	0x6
1451 #define lpfc_mbx_wq_create_wqe_count_SHIFT	16
1452 #define lpfc_mbx_wq_create_wqe_count_MASK	0x0000FFFF
1453 #define lpfc_mbx_wq_create_wqe_count_WORD	word1
1454 			uint32_t word2;
1455 			struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1456 		} request_1;
1457 		struct {
1458 			uint32_t word0;
1459 #define lpfc_mbx_wq_create_q_id_SHIFT	0
1460 #define lpfc_mbx_wq_create_q_id_MASK	0x0000FFFF
1461 #define lpfc_mbx_wq_create_q_id_WORD	word0
1462 			uint32_t doorbell_offset;
1463 			uint32_t word2;
1464 #define lpfc_mbx_wq_create_bar_set_SHIFT	0
1465 #define lpfc_mbx_wq_create_bar_set_MASK		0x0000FFFF
1466 #define lpfc_mbx_wq_create_bar_set_WORD		word2
1467 #define WQ_PCI_BAR_0_AND_1	0x00
1468 #define WQ_PCI_BAR_2_AND_3	0x01
1469 #define WQ_PCI_BAR_4_AND_5	0x02
1470 #define lpfc_mbx_wq_create_db_format_SHIFT	16
1471 #define lpfc_mbx_wq_create_db_format_MASK	0x0000FFFF
1472 #define lpfc_mbx_wq_create_db_format_WORD	word2
1473 		} response;
1474 		struct {
1475 			uint32_t word0;
1476 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT	31
1477 #define lpfc_mbx_wq_create_dpp_rsp_MASK		0x00000001
1478 #define lpfc_mbx_wq_create_dpp_rsp_WORD		word0
1479 #define lpfc_mbx_wq_create_v1_q_id_SHIFT	0
1480 #define lpfc_mbx_wq_create_v1_q_id_MASK		0x0000FFFF
1481 #define lpfc_mbx_wq_create_v1_q_id_WORD		word0
1482 			uint32_t word1;
1483 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT	0
1484 #define lpfc_mbx_wq_create_v1_bar_set_MASK	0x0000000F
1485 #define lpfc_mbx_wq_create_v1_bar_set_WORD	word1
1486 			uint32_t doorbell_offset;
1487 			uint32_t word3;
1488 #define lpfc_mbx_wq_create_dpp_id_SHIFT		16
1489 #define lpfc_mbx_wq_create_dpp_id_MASK		0x0000001F
1490 #define lpfc_mbx_wq_create_dpp_id_WORD		word3
1491 #define lpfc_mbx_wq_create_dpp_bar_SHIFT	0
1492 #define lpfc_mbx_wq_create_dpp_bar_MASK		0x0000000F
1493 #define lpfc_mbx_wq_create_dpp_bar_WORD		word3
1494 			uint32_t dpp_offset;
1495 		} response_1;
1496 	} u;
1497 };
1498 
1499 struct lpfc_mbx_wq_destroy {
1500 	struct mbox_header header;
1501 	union {
1502 		struct {
1503 			uint32_t word0;
1504 #define lpfc_mbx_wq_destroy_q_id_SHIFT	0
1505 #define lpfc_mbx_wq_destroy_q_id_MASK	0x0000FFFF
1506 #define lpfc_mbx_wq_destroy_q_id_WORD	word0
1507 		} request;
1508 		struct {
1509 			uint32_t word0;
1510 		} response;
1511 	} u;
1512 };
1513 
1514 #define LPFC_HDR_BUF_SIZE 128
1515 #define LPFC_DATA_BUF_SIZE 2048
1516 #define LPFC_NVMET_DATA_BUF_SIZE 128
1517 struct rq_context {
1518 	uint32_t word0;
1519 #define lpfc_rq_context_rqe_count_SHIFT	16	/* Version 0 Only */
1520 #define lpfc_rq_context_rqe_count_MASK	0x0000000F
1521 #define lpfc_rq_context_rqe_count_WORD	word0
1522 #define LPFC_RQ_RING_SIZE_512		9	/* 512 entries */
1523 #define LPFC_RQ_RING_SIZE_1024		10	/* 1024 entries */
1524 #define LPFC_RQ_RING_SIZE_2048		11	/* 2048 entries */
1525 #define LPFC_RQ_RING_SIZE_4096		12	/* 4096 entries */
1526 #define lpfc_rq_context_rqe_count_1_SHIFT	16	/* Version 1-2 Only */
1527 #define lpfc_rq_context_rqe_count_1_MASK	0x0000FFFF
1528 #define lpfc_rq_context_rqe_count_1_WORD	word0
1529 #define lpfc_rq_context_rqe_size_SHIFT	8		/* Version 1-2 Only */
1530 #define lpfc_rq_context_rqe_size_MASK	0x0000000F
1531 #define lpfc_rq_context_rqe_size_WORD	word0
1532 #define LPFC_RQE_SIZE_8		2
1533 #define LPFC_RQE_SIZE_16	3
1534 #define LPFC_RQE_SIZE_32	4
1535 #define LPFC_RQE_SIZE_64	5
1536 #define LPFC_RQE_SIZE_128	6
1537 #define lpfc_rq_context_page_size_SHIFT	0		/* Version 1 Only */
1538 #define lpfc_rq_context_page_size_MASK	0x000000FF
1539 #define lpfc_rq_context_page_size_WORD	word0
1540 #define	LPFC_RQ_PAGE_SIZE_4096	0x1
1541 	uint32_t word1;
1542 #define lpfc_rq_context_data_size_SHIFT	16		/* Version 2 Only */
1543 #define lpfc_rq_context_data_size_MASK	0x0000FFFF
1544 #define lpfc_rq_context_data_size_WORD	word1
1545 #define lpfc_rq_context_hdr_size_SHIFT	0		/* Version 2 Only */
1546 #define lpfc_rq_context_hdr_size_MASK	0x0000FFFF
1547 #define lpfc_rq_context_hdr_size_WORD	word1
1548 	uint32_t word2;
1549 #define lpfc_rq_context_cq_id_SHIFT	16
1550 #define lpfc_rq_context_cq_id_MASK	0x000003FF
1551 #define lpfc_rq_context_cq_id_WORD	word2
1552 #define lpfc_rq_context_buf_size_SHIFT	0
1553 #define lpfc_rq_context_buf_size_MASK	0x0000FFFF
1554 #define lpfc_rq_context_buf_size_WORD	word2
1555 #define lpfc_rq_context_base_cq_SHIFT	0		/* Version 2 Only */
1556 #define lpfc_rq_context_base_cq_MASK	0x0000FFFF
1557 #define lpfc_rq_context_base_cq_WORD	word2
1558 	uint32_t buffer_size;				/* Version 1 Only */
1559 };
1560 
1561 struct lpfc_mbx_rq_create {
1562 	struct mbox_header header;
1563 	union {
1564 		struct {
1565 			uint32_t word0;
1566 #define lpfc_mbx_rq_create_num_pages_SHIFT	0
1567 #define lpfc_mbx_rq_create_num_pages_MASK	0x0000FFFF
1568 #define lpfc_mbx_rq_create_num_pages_WORD	word0
1569 #define lpfc_mbx_rq_create_dua_SHIFT		16
1570 #define lpfc_mbx_rq_create_dua_MASK		0x00000001
1571 #define lpfc_mbx_rq_create_dua_WORD		word0
1572 #define lpfc_mbx_rq_create_bqu_SHIFT		17
1573 #define lpfc_mbx_rq_create_bqu_MASK		0x00000001
1574 #define lpfc_mbx_rq_create_bqu_WORD		word0
1575 #define lpfc_mbx_rq_create_ulp_num_SHIFT	24
1576 #define lpfc_mbx_rq_create_ulp_num_MASK		0x000000FF
1577 #define lpfc_mbx_rq_create_ulp_num_WORD		word0
1578 			struct rq_context context;
1579 			struct dma_address page[LPFC_MAX_RQ_PAGE];
1580 		} request;
1581 		struct {
1582 			uint32_t word0;
1583 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT	16
1584 #define lpfc_mbx_rq_create_q_cnt_v2_MASK	0x0000FFFF
1585 #define lpfc_mbx_rq_create_q_cnt_v2_WORD	word0
1586 #define lpfc_mbx_rq_create_q_id_SHIFT		0
1587 #define lpfc_mbx_rq_create_q_id_MASK		0x0000FFFF
1588 #define lpfc_mbx_rq_create_q_id_WORD		word0
1589 			uint32_t doorbell_offset;
1590 			uint32_t word2;
1591 #define lpfc_mbx_rq_create_bar_set_SHIFT	0
1592 #define lpfc_mbx_rq_create_bar_set_MASK		0x0000FFFF
1593 #define lpfc_mbx_rq_create_bar_set_WORD		word2
1594 #define lpfc_mbx_rq_create_db_format_SHIFT	16
1595 #define lpfc_mbx_rq_create_db_format_MASK	0x0000FFFF
1596 #define lpfc_mbx_rq_create_db_format_WORD	word2
1597 		} response;
1598 	} u;
1599 };
1600 
1601 struct lpfc_mbx_rq_create_v2 {
1602 	union  lpfc_sli4_cfg_shdr cfg_shdr;
1603 	union {
1604 		struct {
1605 			uint32_t word0;
1606 #define lpfc_mbx_rq_create_num_pages_SHIFT	0
1607 #define lpfc_mbx_rq_create_num_pages_MASK	0x0000FFFF
1608 #define lpfc_mbx_rq_create_num_pages_WORD	word0
1609 #define lpfc_mbx_rq_create_rq_cnt_SHIFT		16
1610 #define lpfc_mbx_rq_create_rq_cnt_MASK		0x000000FF
1611 #define lpfc_mbx_rq_create_rq_cnt_WORD		word0
1612 #define lpfc_mbx_rq_create_dua_SHIFT		16
1613 #define lpfc_mbx_rq_create_dua_MASK		0x00000001
1614 #define lpfc_mbx_rq_create_dua_WORD		word0
1615 #define lpfc_mbx_rq_create_bqu_SHIFT		17
1616 #define lpfc_mbx_rq_create_bqu_MASK		0x00000001
1617 #define lpfc_mbx_rq_create_bqu_WORD		word0
1618 #define lpfc_mbx_rq_create_ulp_num_SHIFT	24
1619 #define lpfc_mbx_rq_create_ulp_num_MASK		0x000000FF
1620 #define lpfc_mbx_rq_create_ulp_num_WORD		word0
1621 #define lpfc_mbx_rq_create_dim_SHIFT		29
1622 #define lpfc_mbx_rq_create_dim_MASK		0x00000001
1623 #define lpfc_mbx_rq_create_dim_WORD		word0
1624 #define lpfc_mbx_rq_create_dfd_SHIFT		30
1625 #define lpfc_mbx_rq_create_dfd_MASK		0x00000001
1626 #define lpfc_mbx_rq_create_dfd_WORD		word0
1627 #define lpfc_mbx_rq_create_dnb_SHIFT		31
1628 #define lpfc_mbx_rq_create_dnb_MASK		0x00000001
1629 #define lpfc_mbx_rq_create_dnb_WORD		word0
1630 			struct rq_context context;
1631 			struct dma_address page[1];
1632 		} request;
1633 		struct {
1634 			uint32_t word0;
1635 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT	16
1636 #define lpfc_mbx_rq_create_q_cnt_v2_MASK	0x0000FFFF
1637 #define lpfc_mbx_rq_create_q_cnt_v2_WORD	word0
1638 #define lpfc_mbx_rq_create_q_id_SHIFT		0
1639 #define lpfc_mbx_rq_create_q_id_MASK		0x0000FFFF
1640 #define lpfc_mbx_rq_create_q_id_WORD		word0
1641 			uint32_t doorbell_offset;
1642 			uint32_t word2;
1643 #define lpfc_mbx_rq_create_bar_set_SHIFT	0
1644 #define lpfc_mbx_rq_create_bar_set_MASK		0x0000FFFF
1645 #define lpfc_mbx_rq_create_bar_set_WORD		word2
1646 #define lpfc_mbx_rq_create_db_format_SHIFT	16
1647 #define lpfc_mbx_rq_create_db_format_MASK	0x0000FFFF
1648 #define lpfc_mbx_rq_create_db_format_WORD	word2
1649 		} response;
1650 	} u;
1651 };
1652 
1653 struct lpfc_mbx_rq_destroy {
1654 	struct mbox_header header;
1655 	union {
1656 		struct {
1657 			uint32_t word0;
1658 #define lpfc_mbx_rq_destroy_q_id_SHIFT	0
1659 #define lpfc_mbx_rq_destroy_q_id_MASK	0x0000FFFF
1660 #define lpfc_mbx_rq_destroy_q_id_WORD	word0
1661 		} request;
1662 		struct {
1663 			uint32_t word0;
1664 		} response;
1665 	} u;
1666 };
1667 
1668 struct mq_context {
1669 	uint32_t word0;
1670 #define lpfc_mq_context_cq_id_SHIFT	22 	/* Version 0 Only */
1671 #define lpfc_mq_context_cq_id_MASK	0x000003FF
1672 #define lpfc_mq_context_cq_id_WORD	word0
1673 #define lpfc_mq_context_ring_size_SHIFT	16
1674 #define lpfc_mq_context_ring_size_MASK	0x0000000F
1675 #define lpfc_mq_context_ring_size_WORD	word0
1676 #define LPFC_MQ_RING_SIZE_16		0x5
1677 #define LPFC_MQ_RING_SIZE_32		0x6
1678 #define LPFC_MQ_RING_SIZE_64		0x7
1679 #define LPFC_MQ_RING_SIZE_128		0x8
1680 	uint32_t word1;
1681 #define lpfc_mq_context_valid_SHIFT	31
1682 #define lpfc_mq_context_valid_MASK	0x00000001
1683 #define lpfc_mq_context_valid_WORD	word1
1684 	uint32_t reserved2;
1685 	uint32_t reserved3;
1686 };
1687 
1688 struct lpfc_mbx_mq_create {
1689 	struct mbox_header header;
1690 	union {
1691 		struct {
1692 			uint32_t word0;
1693 #define lpfc_mbx_mq_create_num_pages_SHIFT	0
1694 #define lpfc_mbx_mq_create_num_pages_MASK	0x0000FFFF
1695 #define lpfc_mbx_mq_create_num_pages_WORD	word0
1696 			struct mq_context context;
1697 			struct dma_address page[LPFC_MAX_MQ_PAGE];
1698 		} request;
1699 		struct {
1700 			uint32_t word0;
1701 #define lpfc_mbx_mq_create_q_id_SHIFT	0
1702 #define lpfc_mbx_mq_create_q_id_MASK	0x0000FFFF
1703 #define lpfc_mbx_mq_create_q_id_WORD	word0
1704 		} response;
1705 	} u;
1706 };
1707 
1708 struct lpfc_mbx_mq_create_ext {
1709 	struct mbox_header header;
1710 	union {
1711 		struct {
1712 			uint32_t word0;
1713 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT	0
1714 #define lpfc_mbx_mq_create_ext_num_pages_MASK	0x0000FFFF
1715 #define lpfc_mbx_mq_create_ext_num_pages_WORD	word0
1716 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT	16	/* Version 1 Only */
1717 #define lpfc_mbx_mq_create_ext_cq_id_MASK	0x0000FFFF
1718 #define lpfc_mbx_mq_create_ext_cq_id_WORD	word0
1719 			uint32_t async_evt_bmap;
1720 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT	LPFC_TRAILER_CODE_LINK
1721 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK	0x00000001
1722 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD	async_evt_bmap
1723 #define LPFC_EVT_CODE_LINK_NO_LINK	0x0
1724 #define LPFC_EVT_CODE_LINK_10_MBIT	0x1
1725 #define LPFC_EVT_CODE_LINK_100_MBIT	0x2
1726 #define LPFC_EVT_CODE_LINK_1_GBIT	0x3
1727 #define LPFC_EVT_CODE_LINK_10_GBIT	0x4
1728 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT	LPFC_TRAILER_CODE_FCOE
1729 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK	0x00000001
1730 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD	async_evt_bmap
1731 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT	LPFC_TRAILER_CODE_GRP5
1732 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK	0x00000001
1733 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD	async_evt_bmap
1734 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT	LPFC_TRAILER_CODE_FC
1735 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK	0x00000001
1736 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD	async_evt_bmap
1737 #define LPFC_EVT_CODE_FC_NO_LINK	0x0
1738 #define LPFC_EVT_CODE_FC_1_GBAUD	0x1
1739 #define LPFC_EVT_CODE_FC_2_GBAUD	0x2
1740 #define LPFC_EVT_CODE_FC_4_GBAUD	0x4
1741 #define LPFC_EVT_CODE_FC_8_GBAUD	0x8
1742 #define LPFC_EVT_CODE_FC_10_GBAUD	0xA
1743 #define LPFC_EVT_CODE_FC_16_GBAUD	0x10
1744 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT	LPFC_TRAILER_CODE_SLI
1745 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK	0x00000001
1746 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD	async_evt_bmap
1747 			struct mq_context context;
1748 			struct dma_address page[LPFC_MAX_MQ_PAGE];
1749 		} request;
1750 		struct {
1751 			uint32_t word0;
1752 #define lpfc_mbx_mq_create_q_id_SHIFT	0
1753 #define lpfc_mbx_mq_create_q_id_MASK	0x0000FFFF
1754 #define lpfc_mbx_mq_create_q_id_WORD	word0
1755 		} response;
1756 	} u;
1757 #define LPFC_ASYNC_EVENT_LINK_STATE	0x2
1758 #define LPFC_ASYNC_EVENT_FCF_STATE	0x4
1759 #define LPFC_ASYNC_EVENT_GROUP5		0x20
1760 };
1761 
1762 struct lpfc_mbx_mq_destroy {
1763 	struct mbox_header header;
1764 	union {
1765 		struct {
1766 			uint32_t word0;
1767 #define lpfc_mbx_mq_destroy_q_id_SHIFT	0
1768 #define lpfc_mbx_mq_destroy_q_id_MASK	0x0000FFFF
1769 #define lpfc_mbx_mq_destroy_q_id_WORD	word0
1770 		} request;
1771 		struct {
1772 			uint32_t word0;
1773 		} response;
1774 	} u;
1775 };
1776 
1777 /* Start Gen 2 SLI4 Mailbox definitions: */
1778 
1779 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1780 #define LPFC_RSC_TYPE_FCOE_VFI	0x20
1781 #define LPFC_RSC_TYPE_FCOE_VPI	0x21
1782 #define LPFC_RSC_TYPE_FCOE_RPI	0x22
1783 #define LPFC_RSC_TYPE_FCOE_XRI	0x23
1784 
1785 struct lpfc_mbx_get_rsrc_extent_info {
1786 	struct mbox_header header;
1787 	union {
1788 		struct {
1789 			uint32_t word4;
1790 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT	0
1791 #define lpfc_mbx_get_rsrc_extent_info_type_MASK		0x0000FFFF
1792 #define lpfc_mbx_get_rsrc_extent_info_type_WORD		word4
1793 		} req;
1794 		struct {
1795 			uint32_t word4;
1796 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT		0
1797 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK		0x0000FFFF
1798 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD		word4
1799 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT	16
1800 #define lpfc_mbx_get_rsrc_extent_info_size_MASK		0x0000FFFF
1801 #define lpfc_mbx_get_rsrc_extent_info_size_WORD		word4
1802 		} rsp;
1803 	} u;
1804 };
1805 
1806 struct lpfc_mbx_query_fw_config {
1807 	struct mbox_header header;
1808 	struct {
1809 		uint32_t config_number;
1810 #define	LPFC_FC_FCOE		0x00000007
1811 		uint32_t asic_revision;
1812 		uint32_t physical_port;
1813 		uint32_t function_mode;
1814 #define LPFC_FCOE_INI_MODE	0x00000040
1815 #define LPFC_FCOE_TGT_MODE	0x00000080
1816 #define LPFC_DUA_MODE		0x00000800
1817 		uint32_t ulp0_mode;
1818 #define LPFC_ULP_FCOE_INIT_MODE	0x00000040
1819 #define LPFC_ULP_FCOE_TGT_MODE	0x00000080
1820 		uint32_t ulp0_nap_words[12];
1821 		uint32_t ulp1_mode;
1822 		uint32_t ulp1_nap_words[12];
1823 		uint32_t function_capabilities;
1824 		uint32_t cqid_base;
1825 		uint32_t cqid_tot;
1826 		uint32_t eqid_base;
1827 		uint32_t eqid_tot;
1828 		uint32_t ulp0_nap2_words[2];
1829 		uint32_t ulp1_nap2_words[2];
1830 	} rsp;
1831 };
1832 
1833 struct lpfc_mbx_set_beacon_config {
1834 	struct mbox_header header;
1835 	uint32_t word4;
1836 #define lpfc_mbx_set_beacon_port_num_SHIFT		0
1837 #define lpfc_mbx_set_beacon_port_num_MASK		0x0000003F
1838 #define lpfc_mbx_set_beacon_port_num_WORD		word4
1839 #define lpfc_mbx_set_beacon_port_type_SHIFT		6
1840 #define lpfc_mbx_set_beacon_port_type_MASK		0x00000003
1841 #define lpfc_mbx_set_beacon_port_type_WORD		word4
1842 #define lpfc_mbx_set_beacon_state_SHIFT			8
1843 #define lpfc_mbx_set_beacon_state_MASK			0x000000FF
1844 #define lpfc_mbx_set_beacon_state_WORD			word4
1845 #define lpfc_mbx_set_beacon_duration_SHIFT		16
1846 #define lpfc_mbx_set_beacon_duration_MASK		0x000000FF
1847 #define lpfc_mbx_set_beacon_duration_WORD		word4
1848 
1849 /* COMMON_SET_BEACON_CONFIG_V1 */
1850 #define lpfc_mbx_set_beacon_duration_v1_SHIFT		16
1851 #define lpfc_mbx_set_beacon_duration_v1_MASK		0x0000FFFF
1852 #define lpfc_mbx_set_beacon_duration_v1_WORD		word4
1853 	uint32_t word5;  /* RESERVED  */
1854 };
1855 
1856 struct lpfc_id_range {
1857 	uint32_t word5;
1858 #define lpfc_mbx_rsrc_id_word4_0_SHIFT	0
1859 #define lpfc_mbx_rsrc_id_word4_0_MASK	0x0000FFFF
1860 #define lpfc_mbx_rsrc_id_word4_0_WORD	word5
1861 #define lpfc_mbx_rsrc_id_word4_1_SHIFT	16
1862 #define lpfc_mbx_rsrc_id_word4_1_MASK	0x0000FFFF
1863 #define lpfc_mbx_rsrc_id_word4_1_WORD	word5
1864 };
1865 
1866 struct lpfc_mbx_set_link_diag_state {
1867 	struct mbox_header header;
1868 	union {
1869 		struct {
1870 			uint32_t word0;
1871 #define lpfc_mbx_set_diag_state_diag_SHIFT	0
1872 #define lpfc_mbx_set_diag_state_diag_MASK	0x00000001
1873 #define lpfc_mbx_set_diag_state_diag_WORD	word0
1874 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT	2
1875 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK	0x00000001
1876 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD	word0
1877 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE	0
1878 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE		1
1879 #define lpfc_mbx_set_diag_state_link_num_SHIFT	16
1880 #define lpfc_mbx_set_diag_state_link_num_MASK	0x0000003F
1881 #define lpfc_mbx_set_diag_state_link_num_WORD	word0
1882 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1883 #define lpfc_mbx_set_diag_state_link_type_MASK	0x00000003
1884 #define lpfc_mbx_set_diag_state_link_type_WORD	word0
1885 		} req;
1886 		struct {
1887 			uint32_t word0;
1888 		} rsp;
1889 	} u;
1890 };
1891 
1892 struct lpfc_mbx_set_link_diag_loopback {
1893 	struct mbox_header header;
1894 	union {
1895 		struct {
1896 			uint32_t word0;
1897 #define lpfc_mbx_set_diag_lpbk_type_SHIFT		0
1898 #define lpfc_mbx_set_diag_lpbk_type_MASK		0x00000003
1899 #define lpfc_mbx_set_diag_lpbk_type_WORD		word0
1900 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE			0x0
1901 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL		0x1
1902 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES			0x2
1903 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED	0x3
1904 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT		16
1905 #define lpfc_mbx_set_diag_lpbk_link_num_MASK		0x0000003F
1906 #define lpfc_mbx_set_diag_lpbk_link_num_WORD		word0
1907 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT		22
1908 #define lpfc_mbx_set_diag_lpbk_link_type_MASK		0x00000003
1909 #define lpfc_mbx_set_diag_lpbk_link_type_WORD		word0
1910 		} req;
1911 		struct {
1912 			uint32_t word0;
1913 		} rsp;
1914 	} u;
1915 };
1916 
1917 struct lpfc_mbx_run_link_diag_test {
1918 	struct mbox_header header;
1919 	union {
1920 		struct {
1921 			uint32_t word0;
1922 #define lpfc_mbx_run_diag_test_link_num_SHIFT	16
1923 #define lpfc_mbx_run_diag_test_link_num_MASK	0x0000003F
1924 #define lpfc_mbx_run_diag_test_link_num_WORD	word0
1925 #define lpfc_mbx_run_diag_test_link_type_SHIFT	22
1926 #define lpfc_mbx_run_diag_test_link_type_MASK	0x00000003
1927 #define lpfc_mbx_run_diag_test_link_type_WORD	word0
1928 			uint32_t word1;
1929 #define lpfc_mbx_run_diag_test_test_id_SHIFT	0
1930 #define lpfc_mbx_run_diag_test_test_id_MASK	0x0000FFFF
1931 #define lpfc_mbx_run_diag_test_test_id_WORD	word1
1932 #define lpfc_mbx_run_diag_test_loops_SHIFT	16
1933 #define lpfc_mbx_run_diag_test_loops_MASK	0x0000FFFF
1934 #define lpfc_mbx_run_diag_test_loops_WORD	word1
1935 			uint32_t word2;
1936 #define lpfc_mbx_run_diag_test_test_ver_SHIFT	0
1937 #define lpfc_mbx_run_diag_test_test_ver_MASK	0x0000FFFF
1938 #define lpfc_mbx_run_diag_test_test_ver_WORD	word2
1939 #define lpfc_mbx_run_diag_test_err_act_SHIFT	16
1940 #define lpfc_mbx_run_diag_test_err_act_MASK	0x000000FF
1941 #define lpfc_mbx_run_diag_test_err_act_WORD	word2
1942 		} req;
1943 		struct {
1944 			uint32_t word0;
1945 		} rsp;
1946 	} u;
1947 };
1948 
1949 /*
1950  * struct lpfc_mbx_alloc_rsrc_extents:
1951  * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1952  * 6 words of header + 4 words of shared subcommand header +
1953  * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1954  *
1955  * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1956  * for extents payload.
1957  *
1958  * 212/2 (bytes per extent) = 106 extents.
1959  * 106/2 (extents per word) = 53 words.
1960  * lpfc_id_range id is statically size to 53.
1961  *
1962  * This mailbox definition is used for ALLOC or GET_ALLOCATED
1963  * extent ranges.  For ALLOC, the type and cnt are required.
1964  * For GET_ALLOCATED, only the type is required.
1965  */
1966 struct lpfc_mbx_alloc_rsrc_extents {
1967 	struct mbox_header header;
1968 	union {
1969 		struct {
1970 			uint32_t word4;
1971 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT	0
1972 #define lpfc_mbx_alloc_rsrc_extents_type_MASK	0x0000FFFF
1973 #define lpfc_mbx_alloc_rsrc_extents_type_WORD	word4
1974 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT	16
1975 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK	0x0000FFFF
1976 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD	word4
1977 		} req;
1978 		struct {
1979 			uint32_t word4;
1980 #define lpfc_mbx_rsrc_cnt_SHIFT	0
1981 #define lpfc_mbx_rsrc_cnt_MASK	0x0000FFFF
1982 #define lpfc_mbx_rsrc_cnt_WORD	word4
1983 			struct lpfc_id_range id[53];
1984 		} rsp;
1985 	} u;
1986 };
1987 
1988 /*
1989  * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1990  * structure shares the same SHIFT/MASK/WORD defines provided in the
1991  * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1992  * the structures defined above.  This non-embedded structure provides for the
1993  * maximum number of extents supported by the port.
1994  */
1995 struct lpfc_mbx_nembed_rsrc_extent {
1996 	union  lpfc_sli4_cfg_shdr cfg_shdr;
1997 	uint32_t word4;
1998 	struct lpfc_id_range id;
1999 };
2000 
2001 struct lpfc_mbx_dealloc_rsrc_extents {
2002 	struct mbox_header header;
2003 	struct {
2004 		uint32_t word4;
2005 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT	0
2006 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK		0x0000FFFF
2007 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD		word4
2008 	} req;
2009 
2010 };
2011 
2012 /* Start SLI4 FCoE specific mbox structures. */
2013 
2014 struct lpfc_mbx_post_hdr_tmpl {
2015 	struct mbox_header header;
2016 	uint32_t word10;
2017 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
2018 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
2019 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
2020 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
2021 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
2022 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
2023 	uint32_t rpi_paddr_lo;
2024 	uint32_t rpi_paddr_hi;
2025 };
2026 
2027 struct sli4_sge {	/* SLI-4 */
2028 	uint32_t addr_hi;
2029 	uint32_t addr_lo;
2030 
2031 	uint32_t word2;
2032 #define lpfc_sli4_sge_offset_SHIFT	0
2033 #define lpfc_sli4_sge_offset_MASK	0x07FFFFFF
2034 #define lpfc_sli4_sge_offset_WORD	word2
2035 #define lpfc_sli4_sge_type_SHIFT	27
2036 #define lpfc_sli4_sge_type_MASK		0x0000000F
2037 #define lpfc_sli4_sge_type_WORD		word2
2038 #define LPFC_SGE_TYPE_DATA		0x0
2039 #define LPFC_SGE_TYPE_DIF		0x4
2040 #define LPFC_SGE_TYPE_LSP		0x5
2041 #define LPFC_SGE_TYPE_PEDIF		0x6
2042 #define LPFC_SGE_TYPE_PESEED		0x7
2043 #define LPFC_SGE_TYPE_DISEED		0x8
2044 #define LPFC_SGE_TYPE_ENC		0x9
2045 #define LPFC_SGE_TYPE_ATM		0xA
2046 #define LPFC_SGE_TYPE_SKIP		0xC
2047 #define lpfc_sli4_sge_last_SHIFT	31 /* Last SEG in the SGL sets it */
2048 #define lpfc_sli4_sge_last_MASK		0x00000001
2049 #define lpfc_sli4_sge_last_WORD		word2
2050 	uint32_t sge_len;
2051 };
2052 
2053 struct sli4_hybrid_sgl {
2054 	struct list_head list_node;
2055 	struct sli4_sge *dma_sgl;
2056 	dma_addr_t dma_phys_sgl;
2057 };
2058 
2059 struct fcp_cmd_rsp_buf {
2060 	struct list_head list_node;
2061 
2062 	/* for storing cmd/rsp dma alloc'ed virt_addr */
2063 	struct fcp_cmnd *fcp_cmnd;
2064 	struct fcp_rsp *fcp_rsp;
2065 
2066 	/* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */
2067 	dma_addr_t fcp_cmd_rsp_dma_handle;
2068 };
2069 
2070 struct sli4_sge_diseed {	/* SLI-4 */
2071 	uint32_t ref_tag;
2072 	uint32_t ref_tag_tran;
2073 
2074 	uint32_t word2;
2075 #define lpfc_sli4_sge_dif_apptran_SHIFT	0
2076 #define lpfc_sli4_sge_dif_apptran_MASK	0x0000FFFF
2077 #define lpfc_sli4_sge_dif_apptran_WORD	word2
2078 #define lpfc_sli4_sge_dif_af_SHIFT	24
2079 #define lpfc_sli4_sge_dif_af_MASK	0x00000001
2080 #define lpfc_sli4_sge_dif_af_WORD	word2
2081 #define lpfc_sli4_sge_dif_na_SHIFT	25
2082 #define lpfc_sli4_sge_dif_na_MASK	0x00000001
2083 #define lpfc_sli4_sge_dif_na_WORD	word2
2084 #define lpfc_sli4_sge_dif_hi_SHIFT	26
2085 #define lpfc_sli4_sge_dif_hi_MASK	0x00000001
2086 #define lpfc_sli4_sge_dif_hi_WORD	word2
2087 #define lpfc_sli4_sge_dif_type_SHIFT	27
2088 #define lpfc_sli4_sge_dif_type_MASK	0x0000000F
2089 #define lpfc_sli4_sge_dif_type_WORD	word2
2090 #define lpfc_sli4_sge_dif_last_SHIFT	31 /* Last SEG in the SGL sets it */
2091 #define lpfc_sli4_sge_dif_last_MASK	0x00000001
2092 #define lpfc_sli4_sge_dif_last_WORD	word2
2093 	uint32_t word3;
2094 #define lpfc_sli4_sge_dif_apptag_SHIFT	0
2095 #define lpfc_sli4_sge_dif_apptag_MASK	0x0000FFFF
2096 #define lpfc_sli4_sge_dif_apptag_WORD	word3
2097 #define lpfc_sli4_sge_dif_bs_SHIFT	16
2098 #define lpfc_sli4_sge_dif_bs_MASK	0x00000007
2099 #define lpfc_sli4_sge_dif_bs_WORD	word3
2100 #define lpfc_sli4_sge_dif_ai_SHIFT	19
2101 #define lpfc_sli4_sge_dif_ai_MASK	0x00000001
2102 #define lpfc_sli4_sge_dif_ai_WORD	word3
2103 #define lpfc_sli4_sge_dif_me_SHIFT	20
2104 #define lpfc_sli4_sge_dif_me_MASK	0x00000001
2105 #define lpfc_sli4_sge_dif_me_WORD	word3
2106 #define lpfc_sli4_sge_dif_re_SHIFT	21
2107 #define lpfc_sli4_sge_dif_re_MASK	0x00000001
2108 #define lpfc_sli4_sge_dif_re_WORD	word3
2109 #define lpfc_sli4_sge_dif_ce_SHIFT	22
2110 #define lpfc_sli4_sge_dif_ce_MASK	0x00000001
2111 #define lpfc_sli4_sge_dif_ce_WORD	word3
2112 #define lpfc_sli4_sge_dif_nr_SHIFT	23
2113 #define lpfc_sli4_sge_dif_nr_MASK	0x00000001
2114 #define lpfc_sli4_sge_dif_nr_WORD	word3
2115 #define lpfc_sli4_sge_dif_oprx_SHIFT	24
2116 #define lpfc_sli4_sge_dif_oprx_MASK	0x0000000F
2117 #define lpfc_sli4_sge_dif_oprx_WORD	word3
2118 #define lpfc_sli4_sge_dif_optx_SHIFT	28
2119 #define lpfc_sli4_sge_dif_optx_MASK	0x0000000F
2120 #define lpfc_sli4_sge_dif_optx_WORD	word3
2121 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
2122 };
2123 
2124 struct fcf_record {
2125 	uint32_t max_rcv_size;
2126 	uint32_t fka_adv_period;
2127 	uint32_t fip_priority;
2128 	uint32_t word3;
2129 #define lpfc_fcf_record_mac_0_SHIFT		0
2130 #define lpfc_fcf_record_mac_0_MASK		0x000000FF
2131 #define lpfc_fcf_record_mac_0_WORD		word3
2132 #define lpfc_fcf_record_mac_1_SHIFT		8
2133 #define lpfc_fcf_record_mac_1_MASK		0x000000FF
2134 #define lpfc_fcf_record_mac_1_WORD		word3
2135 #define lpfc_fcf_record_mac_2_SHIFT		16
2136 #define lpfc_fcf_record_mac_2_MASK		0x000000FF
2137 #define lpfc_fcf_record_mac_2_WORD		word3
2138 #define lpfc_fcf_record_mac_3_SHIFT		24
2139 #define lpfc_fcf_record_mac_3_MASK		0x000000FF
2140 #define lpfc_fcf_record_mac_3_WORD		word3
2141 	uint32_t word4;
2142 #define lpfc_fcf_record_mac_4_SHIFT		0
2143 #define lpfc_fcf_record_mac_4_MASK		0x000000FF
2144 #define lpfc_fcf_record_mac_4_WORD		word4
2145 #define lpfc_fcf_record_mac_5_SHIFT		8
2146 #define lpfc_fcf_record_mac_5_MASK		0x000000FF
2147 #define lpfc_fcf_record_mac_5_WORD		word4
2148 #define lpfc_fcf_record_fcf_avail_SHIFT		16
2149 #define lpfc_fcf_record_fcf_avail_MASK		0x000000FF
2150 #define lpfc_fcf_record_fcf_avail_WORD		word4
2151 #define lpfc_fcf_record_mac_addr_prov_SHIFT	24
2152 #define lpfc_fcf_record_mac_addr_prov_MASK	0x000000FF
2153 #define lpfc_fcf_record_mac_addr_prov_WORD	word4
2154 #define LPFC_FCF_FPMA           1 	/* Fabric Provided MAC Address */
2155 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
2156 	uint32_t word5;
2157 #define lpfc_fcf_record_fab_name_0_SHIFT	0
2158 #define lpfc_fcf_record_fab_name_0_MASK		0x000000FF
2159 #define lpfc_fcf_record_fab_name_0_WORD		word5
2160 #define lpfc_fcf_record_fab_name_1_SHIFT	8
2161 #define lpfc_fcf_record_fab_name_1_MASK		0x000000FF
2162 #define lpfc_fcf_record_fab_name_1_WORD		word5
2163 #define lpfc_fcf_record_fab_name_2_SHIFT	16
2164 #define lpfc_fcf_record_fab_name_2_MASK		0x000000FF
2165 #define lpfc_fcf_record_fab_name_2_WORD		word5
2166 #define lpfc_fcf_record_fab_name_3_SHIFT	24
2167 #define lpfc_fcf_record_fab_name_3_MASK		0x000000FF
2168 #define lpfc_fcf_record_fab_name_3_WORD		word5
2169 	uint32_t word6;
2170 #define lpfc_fcf_record_fab_name_4_SHIFT	0
2171 #define lpfc_fcf_record_fab_name_4_MASK		0x000000FF
2172 #define lpfc_fcf_record_fab_name_4_WORD		word6
2173 #define lpfc_fcf_record_fab_name_5_SHIFT	8
2174 #define lpfc_fcf_record_fab_name_5_MASK		0x000000FF
2175 #define lpfc_fcf_record_fab_name_5_WORD		word6
2176 #define lpfc_fcf_record_fab_name_6_SHIFT	16
2177 #define lpfc_fcf_record_fab_name_6_MASK		0x000000FF
2178 #define lpfc_fcf_record_fab_name_6_WORD		word6
2179 #define lpfc_fcf_record_fab_name_7_SHIFT	24
2180 #define lpfc_fcf_record_fab_name_7_MASK		0x000000FF
2181 #define lpfc_fcf_record_fab_name_7_WORD		word6
2182 	uint32_t word7;
2183 #define lpfc_fcf_record_fc_map_0_SHIFT		0
2184 #define lpfc_fcf_record_fc_map_0_MASK		0x000000FF
2185 #define lpfc_fcf_record_fc_map_0_WORD		word7
2186 #define lpfc_fcf_record_fc_map_1_SHIFT		8
2187 #define lpfc_fcf_record_fc_map_1_MASK		0x000000FF
2188 #define lpfc_fcf_record_fc_map_1_WORD		word7
2189 #define lpfc_fcf_record_fc_map_2_SHIFT		16
2190 #define lpfc_fcf_record_fc_map_2_MASK		0x000000FF
2191 #define lpfc_fcf_record_fc_map_2_WORD		word7
2192 #define lpfc_fcf_record_fcf_valid_SHIFT		24
2193 #define lpfc_fcf_record_fcf_valid_MASK		0x00000001
2194 #define lpfc_fcf_record_fcf_valid_WORD		word7
2195 #define lpfc_fcf_record_fcf_fc_SHIFT		25
2196 #define lpfc_fcf_record_fcf_fc_MASK		0x00000001
2197 #define lpfc_fcf_record_fcf_fc_WORD		word7
2198 #define lpfc_fcf_record_fcf_sol_SHIFT		31
2199 #define lpfc_fcf_record_fcf_sol_MASK		0x00000001
2200 #define lpfc_fcf_record_fcf_sol_WORD		word7
2201 	uint32_t word8;
2202 #define lpfc_fcf_record_fcf_index_SHIFT		0
2203 #define lpfc_fcf_record_fcf_index_MASK		0x0000FFFF
2204 #define lpfc_fcf_record_fcf_index_WORD		word8
2205 #define lpfc_fcf_record_fcf_state_SHIFT		16
2206 #define lpfc_fcf_record_fcf_state_MASK		0x0000FFFF
2207 #define lpfc_fcf_record_fcf_state_WORD		word8
2208 	uint8_t vlan_bitmap[512];
2209 	uint32_t word137;
2210 #define lpfc_fcf_record_switch_name_0_SHIFT	0
2211 #define lpfc_fcf_record_switch_name_0_MASK	0x000000FF
2212 #define lpfc_fcf_record_switch_name_0_WORD	word137
2213 #define lpfc_fcf_record_switch_name_1_SHIFT	8
2214 #define lpfc_fcf_record_switch_name_1_MASK	0x000000FF
2215 #define lpfc_fcf_record_switch_name_1_WORD	word137
2216 #define lpfc_fcf_record_switch_name_2_SHIFT	16
2217 #define lpfc_fcf_record_switch_name_2_MASK	0x000000FF
2218 #define lpfc_fcf_record_switch_name_2_WORD	word137
2219 #define lpfc_fcf_record_switch_name_3_SHIFT	24
2220 #define lpfc_fcf_record_switch_name_3_MASK	0x000000FF
2221 #define lpfc_fcf_record_switch_name_3_WORD	word137
2222 	uint32_t word138;
2223 #define lpfc_fcf_record_switch_name_4_SHIFT	0
2224 #define lpfc_fcf_record_switch_name_4_MASK	0x000000FF
2225 #define lpfc_fcf_record_switch_name_4_WORD	word138
2226 #define lpfc_fcf_record_switch_name_5_SHIFT	8
2227 #define lpfc_fcf_record_switch_name_5_MASK	0x000000FF
2228 #define lpfc_fcf_record_switch_name_5_WORD	word138
2229 #define lpfc_fcf_record_switch_name_6_SHIFT	16
2230 #define lpfc_fcf_record_switch_name_6_MASK	0x000000FF
2231 #define lpfc_fcf_record_switch_name_6_WORD	word138
2232 #define lpfc_fcf_record_switch_name_7_SHIFT	24
2233 #define lpfc_fcf_record_switch_name_7_MASK	0x000000FF
2234 #define lpfc_fcf_record_switch_name_7_WORD	word138
2235 };
2236 
2237 struct lpfc_mbx_read_fcf_tbl {
2238 	union lpfc_sli4_cfg_shdr cfg_shdr;
2239 	union {
2240 		struct {
2241 			uint32_t word10;
2242 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT	0
2243 #define lpfc_mbx_read_fcf_tbl_indx_MASK		0x0000FFFF
2244 #define lpfc_mbx_read_fcf_tbl_indx_WORD		word10
2245 		} request;
2246 		struct {
2247 			uint32_t eventag;
2248 		} response;
2249 	} u;
2250 	uint32_t word11;
2251 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT	0
2252 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK	0x0000FFFF
2253 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD	word11
2254 };
2255 
2256 struct lpfc_mbx_add_fcf_tbl_entry {
2257 	union lpfc_sli4_cfg_shdr cfg_shdr;
2258 	uint32_t word10;
2259 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
2260 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
2261 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
2262 	struct lpfc_mbx_sge fcf_sge;
2263 };
2264 
2265 struct lpfc_mbx_del_fcf_tbl_entry {
2266 	struct mbox_header header;
2267 	uint32_t word10;
2268 #define lpfc_mbx_del_fcf_tbl_count_SHIFT	0
2269 #define lpfc_mbx_del_fcf_tbl_count_MASK		0x0000FFFF
2270 #define lpfc_mbx_del_fcf_tbl_count_WORD		word10
2271 #define lpfc_mbx_del_fcf_tbl_index_SHIFT	16
2272 #define lpfc_mbx_del_fcf_tbl_index_MASK		0x0000FFFF
2273 #define lpfc_mbx_del_fcf_tbl_index_WORD		word10
2274 };
2275 
2276 struct lpfc_mbx_redisc_fcf_tbl {
2277 	struct mbox_header header;
2278 	uint32_t word10;
2279 #define lpfc_mbx_redisc_fcf_count_SHIFT		0
2280 #define lpfc_mbx_redisc_fcf_count_MASK		0x0000FFFF
2281 #define lpfc_mbx_redisc_fcf_count_WORD		word10
2282 	uint32_t resvd;
2283 	uint32_t word12;
2284 #define lpfc_mbx_redisc_fcf_index_SHIFT		0
2285 #define lpfc_mbx_redisc_fcf_index_MASK		0x0000FFFF
2286 #define lpfc_mbx_redisc_fcf_index_WORD		word12
2287 };
2288 
2289 /* Status field for embedded SLI_CONFIG mailbox command */
2290 #define STATUS_SUCCESS					0x0
2291 #define STATUS_FAILED 					0x1
2292 #define STATUS_ILLEGAL_REQUEST				0x2
2293 #define STATUS_ILLEGAL_FIELD				0x3
2294 #define STATUS_INSUFFICIENT_BUFFER 			0x4
2295 #define STATUS_UNAUTHORIZED_REQUEST			0x5
2296 #define STATUS_FLASHROM_SAVE_FAILED			0x17
2297 #define STATUS_FLASHROM_RESTORE_FAILED			0x18
2298 #define STATUS_ICCBINDEX_ALLOC_FAILED			0x1a
2299 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 		0x1b
2300 #define STATUS_INVALID_PHY_ADDR_FROM_OSM		0x1c
2301 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM		0x1d
2302 #define STATUS_ASSERT_FAILED				0x1e
2303 #define STATUS_INVALID_SESSION				0x1f
2304 #define STATUS_INVALID_CONNECTION			0x20
2305 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT		0x21
2306 #define STATUS_BTL_NO_FREE_SLOT_PATH			0x24
2307 #define STATUS_BTL_NO_FREE_SLOT_TGTID			0x25
2308 #define STATUS_OSM_DEVSLOT_NOT_FOUND			0x26
2309 #define STATUS_FLASHROM_READ_FAILED			0x27
2310 #define STATUS_POLL_IOCTL_TIMEOUT			0x28
2311 #define STATUS_ERROR_ACITMAIN				0x2a
2312 #define STATUS_REBOOT_REQUIRED				0x2c
2313 #define STATUS_FCF_IN_USE				0x3a
2314 #define STATUS_FCF_TABLE_EMPTY				0x43
2315 
2316 /*
2317  * Additional status field for embedded SLI_CONFIG mailbox
2318  * command.
2319  */
2320 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE		0x67
2321 #define ADD_STATUS_FW_NOT_SUPPORTED			0xEB
2322 #define ADD_STATUS_INVALID_REQUEST			0x4B
2323 
2324 struct lpfc_mbx_sli4_config {
2325 	struct mbox_header header;
2326 };
2327 
2328 struct lpfc_mbx_init_vfi {
2329 	uint32_t word1;
2330 #define lpfc_init_vfi_vr_SHIFT		31
2331 #define lpfc_init_vfi_vr_MASK		0x00000001
2332 #define lpfc_init_vfi_vr_WORD		word1
2333 #define lpfc_init_vfi_vt_SHIFT		30
2334 #define lpfc_init_vfi_vt_MASK		0x00000001
2335 #define lpfc_init_vfi_vt_WORD		word1
2336 #define lpfc_init_vfi_vf_SHIFT		29
2337 #define lpfc_init_vfi_vf_MASK		0x00000001
2338 #define lpfc_init_vfi_vf_WORD		word1
2339 #define lpfc_init_vfi_vp_SHIFT		28
2340 #define lpfc_init_vfi_vp_MASK		0x00000001
2341 #define lpfc_init_vfi_vp_WORD		word1
2342 #define lpfc_init_vfi_vfi_SHIFT		0
2343 #define lpfc_init_vfi_vfi_MASK		0x0000FFFF
2344 #define lpfc_init_vfi_vfi_WORD		word1
2345 	uint32_t word2;
2346 #define lpfc_init_vfi_vpi_SHIFT		16
2347 #define lpfc_init_vfi_vpi_MASK		0x0000FFFF
2348 #define lpfc_init_vfi_vpi_WORD		word2
2349 #define lpfc_init_vfi_fcfi_SHIFT	0
2350 #define lpfc_init_vfi_fcfi_MASK		0x0000FFFF
2351 #define lpfc_init_vfi_fcfi_WORD		word2
2352 	uint32_t word3;
2353 #define lpfc_init_vfi_pri_SHIFT		13
2354 #define lpfc_init_vfi_pri_MASK		0x00000007
2355 #define lpfc_init_vfi_pri_WORD		word3
2356 #define lpfc_init_vfi_vf_id_SHIFT	1
2357 #define lpfc_init_vfi_vf_id_MASK	0x00000FFF
2358 #define lpfc_init_vfi_vf_id_WORD	word3
2359 	uint32_t word4;
2360 #define lpfc_init_vfi_hop_count_SHIFT	24
2361 #define lpfc_init_vfi_hop_count_MASK	0x000000FF
2362 #define lpfc_init_vfi_hop_count_WORD	word4
2363 };
2364 #define MBX_VFI_IN_USE			0x9F02
2365 
2366 
2367 struct lpfc_mbx_reg_vfi {
2368 	uint32_t word1;
2369 #define lpfc_reg_vfi_upd_SHIFT		29
2370 #define lpfc_reg_vfi_upd_MASK		0x00000001
2371 #define lpfc_reg_vfi_upd_WORD		word1
2372 #define lpfc_reg_vfi_vp_SHIFT		28
2373 #define lpfc_reg_vfi_vp_MASK		0x00000001
2374 #define lpfc_reg_vfi_vp_WORD		word1
2375 #define lpfc_reg_vfi_vfi_SHIFT		0
2376 #define lpfc_reg_vfi_vfi_MASK		0x0000FFFF
2377 #define lpfc_reg_vfi_vfi_WORD		word1
2378 	uint32_t word2;
2379 #define lpfc_reg_vfi_vpi_SHIFT		16
2380 #define lpfc_reg_vfi_vpi_MASK		0x0000FFFF
2381 #define lpfc_reg_vfi_vpi_WORD		word2
2382 #define lpfc_reg_vfi_fcfi_SHIFT		0
2383 #define lpfc_reg_vfi_fcfi_MASK		0x0000FFFF
2384 #define lpfc_reg_vfi_fcfi_WORD		word2
2385 	uint32_t wwn[2];
2386 	struct ulp_bde64 bde;
2387 	uint32_t e_d_tov;
2388 	uint32_t r_a_tov;
2389 	uint32_t word10;
2390 #define lpfc_reg_vfi_nport_id_SHIFT	0
2391 #define lpfc_reg_vfi_nport_id_MASK	0x00FFFFFF
2392 #define lpfc_reg_vfi_nport_id_WORD	word10
2393 #define lpfc_reg_vfi_bbcr_SHIFT		27
2394 #define lpfc_reg_vfi_bbcr_MASK		0x00000001
2395 #define lpfc_reg_vfi_bbcr_WORD		word10
2396 #define lpfc_reg_vfi_bbscn_SHIFT	28
2397 #define lpfc_reg_vfi_bbscn_MASK		0x0000000F
2398 #define lpfc_reg_vfi_bbscn_WORD		word10
2399 };
2400 
2401 struct lpfc_mbx_init_vpi {
2402 	uint32_t word1;
2403 #define lpfc_init_vpi_vfi_SHIFT		16
2404 #define lpfc_init_vpi_vfi_MASK		0x0000FFFF
2405 #define lpfc_init_vpi_vfi_WORD		word1
2406 #define lpfc_init_vpi_vpi_SHIFT		0
2407 #define lpfc_init_vpi_vpi_MASK		0x0000FFFF
2408 #define lpfc_init_vpi_vpi_WORD		word1
2409 };
2410 
2411 struct lpfc_mbx_read_vpi {
2412 	uint32_t word1_rsvd;
2413 	uint32_t word2;
2414 #define lpfc_mbx_read_vpi_vnportid_SHIFT	0
2415 #define lpfc_mbx_read_vpi_vnportid_MASK		0x00FFFFFF
2416 #define lpfc_mbx_read_vpi_vnportid_WORD		word2
2417 	uint32_t word3_rsvd;
2418 	uint32_t word4;
2419 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT	0
2420 #define lpfc_mbx_read_vpi_acq_alpa_MASK		0x000000FF
2421 #define lpfc_mbx_read_vpi_acq_alpa_WORD		word4
2422 #define lpfc_mbx_read_vpi_pb_SHIFT		15
2423 #define lpfc_mbx_read_vpi_pb_MASK		0x00000001
2424 #define lpfc_mbx_read_vpi_pb_WORD		word4
2425 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT	16
2426 #define lpfc_mbx_read_vpi_spec_alpa_MASK	0x000000FF
2427 #define lpfc_mbx_read_vpi_spec_alpa_WORD	word4
2428 #define lpfc_mbx_read_vpi_ns_SHIFT		30
2429 #define lpfc_mbx_read_vpi_ns_MASK		0x00000001
2430 #define lpfc_mbx_read_vpi_ns_WORD		word4
2431 #define lpfc_mbx_read_vpi_hl_SHIFT		31
2432 #define lpfc_mbx_read_vpi_hl_MASK		0x00000001
2433 #define lpfc_mbx_read_vpi_hl_WORD		word4
2434 	uint32_t word5_rsvd;
2435 	uint32_t word6;
2436 #define lpfc_mbx_read_vpi_vpi_SHIFT		0
2437 #define lpfc_mbx_read_vpi_vpi_MASK		0x0000FFFF
2438 #define lpfc_mbx_read_vpi_vpi_WORD		word6
2439 	uint32_t word7;
2440 #define lpfc_mbx_read_vpi_mac_0_SHIFT		0
2441 #define lpfc_mbx_read_vpi_mac_0_MASK		0x000000FF
2442 #define lpfc_mbx_read_vpi_mac_0_WORD		word7
2443 #define lpfc_mbx_read_vpi_mac_1_SHIFT		8
2444 #define lpfc_mbx_read_vpi_mac_1_MASK		0x000000FF
2445 #define lpfc_mbx_read_vpi_mac_1_WORD		word7
2446 #define lpfc_mbx_read_vpi_mac_2_SHIFT		16
2447 #define lpfc_mbx_read_vpi_mac_2_MASK		0x000000FF
2448 #define lpfc_mbx_read_vpi_mac_2_WORD		word7
2449 #define lpfc_mbx_read_vpi_mac_3_SHIFT		24
2450 #define lpfc_mbx_read_vpi_mac_3_MASK		0x000000FF
2451 #define lpfc_mbx_read_vpi_mac_3_WORD		word7
2452 	uint32_t word8;
2453 #define lpfc_mbx_read_vpi_mac_4_SHIFT		0
2454 #define lpfc_mbx_read_vpi_mac_4_MASK		0x000000FF
2455 #define lpfc_mbx_read_vpi_mac_4_WORD		word8
2456 #define lpfc_mbx_read_vpi_mac_5_SHIFT		8
2457 #define lpfc_mbx_read_vpi_mac_5_MASK		0x000000FF
2458 #define lpfc_mbx_read_vpi_mac_5_WORD		word8
2459 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT	16
2460 #define lpfc_mbx_read_vpi_vlan_tag_MASK		0x00000FFF
2461 #define lpfc_mbx_read_vpi_vlan_tag_WORD		word8
2462 #define lpfc_mbx_read_vpi_vv_SHIFT		28
2463 #define lpfc_mbx_read_vpi_vv_MASK		0x0000001
2464 #define lpfc_mbx_read_vpi_vv_WORD		word8
2465 };
2466 
2467 struct lpfc_mbx_unreg_vfi {
2468 	uint32_t word1_rsvd;
2469 	uint32_t word2;
2470 #define lpfc_unreg_vfi_vfi_SHIFT	0
2471 #define lpfc_unreg_vfi_vfi_MASK		0x0000FFFF
2472 #define lpfc_unreg_vfi_vfi_WORD		word2
2473 };
2474 
2475 struct lpfc_mbx_resume_rpi {
2476 	uint32_t word1;
2477 #define lpfc_resume_rpi_index_SHIFT	0
2478 #define lpfc_resume_rpi_index_MASK	0x0000FFFF
2479 #define lpfc_resume_rpi_index_WORD	word1
2480 #define lpfc_resume_rpi_ii_SHIFT	30
2481 #define lpfc_resume_rpi_ii_MASK		0x00000003
2482 #define lpfc_resume_rpi_ii_WORD		word1
2483 #define RESUME_INDEX_RPI		0
2484 #define RESUME_INDEX_VPI		1
2485 #define RESUME_INDEX_VFI		2
2486 #define RESUME_INDEX_FCFI		3
2487 	uint32_t event_tag;
2488 };
2489 
2490 #define REG_FCF_INVALID_QID	0xFFFF
2491 struct lpfc_mbx_reg_fcfi {
2492 	uint32_t word1;
2493 #define lpfc_reg_fcfi_info_index_SHIFT	0
2494 #define lpfc_reg_fcfi_info_index_MASK	0x0000FFFF
2495 #define lpfc_reg_fcfi_info_index_WORD	word1
2496 #define lpfc_reg_fcfi_fcfi_SHIFT	16
2497 #define lpfc_reg_fcfi_fcfi_MASK		0x0000FFFF
2498 #define lpfc_reg_fcfi_fcfi_WORD		word1
2499 	uint32_t word2;
2500 #define lpfc_reg_fcfi_rq_id1_SHIFT	0
2501 #define lpfc_reg_fcfi_rq_id1_MASK	0x0000FFFF
2502 #define lpfc_reg_fcfi_rq_id1_WORD	word2
2503 #define lpfc_reg_fcfi_rq_id0_SHIFT	16
2504 #define lpfc_reg_fcfi_rq_id0_MASK	0x0000FFFF
2505 #define lpfc_reg_fcfi_rq_id0_WORD	word2
2506 	uint32_t word3;
2507 #define lpfc_reg_fcfi_rq_id3_SHIFT	0
2508 #define lpfc_reg_fcfi_rq_id3_MASK	0x0000FFFF
2509 #define lpfc_reg_fcfi_rq_id3_WORD	word3
2510 #define lpfc_reg_fcfi_rq_id2_SHIFT	16
2511 #define lpfc_reg_fcfi_rq_id2_MASK	0x0000FFFF
2512 #define lpfc_reg_fcfi_rq_id2_WORD	word3
2513 	uint32_t word4;
2514 #define lpfc_reg_fcfi_type_match0_SHIFT	24
2515 #define lpfc_reg_fcfi_type_match0_MASK	0x000000FF
2516 #define lpfc_reg_fcfi_type_match0_WORD	word4
2517 #define lpfc_reg_fcfi_type_mask0_SHIFT	16
2518 #define lpfc_reg_fcfi_type_mask0_MASK	0x000000FF
2519 #define lpfc_reg_fcfi_type_mask0_WORD	word4
2520 #define lpfc_reg_fcfi_rctl_match0_SHIFT	8
2521 #define lpfc_reg_fcfi_rctl_match0_MASK	0x000000FF
2522 #define lpfc_reg_fcfi_rctl_match0_WORD	word4
2523 #define lpfc_reg_fcfi_rctl_mask0_SHIFT	0
2524 #define lpfc_reg_fcfi_rctl_mask0_MASK	0x000000FF
2525 #define lpfc_reg_fcfi_rctl_mask0_WORD	word4
2526 	uint32_t word5;
2527 #define lpfc_reg_fcfi_type_match1_SHIFT	24
2528 #define lpfc_reg_fcfi_type_match1_MASK	0x000000FF
2529 #define lpfc_reg_fcfi_type_match1_WORD	word5
2530 #define lpfc_reg_fcfi_type_mask1_SHIFT	16
2531 #define lpfc_reg_fcfi_type_mask1_MASK	0x000000FF
2532 #define lpfc_reg_fcfi_type_mask1_WORD	word5
2533 #define lpfc_reg_fcfi_rctl_match1_SHIFT	8
2534 #define lpfc_reg_fcfi_rctl_match1_MASK	0x000000FF
2535 #define lpfc_reg_fcfi_rctl_match1_WORD	word5
2536 #define lpfc_reg_fcfi_rctl_mask1_SHIFT	0
2537 #define lpfc_reg_fcfi_rctl_mask1_MASK	0x000000FF
2538 #define lpfc_reg_fcfi_rctl_mask1_WORD	word5
2539 	uint32_t word6;
2540 #define lpfc_reg_fcfi_type_match2_SHIFT	24
2541 #define lpfc_reg_fcfi_type_match2_MASK	0x000000FF
2542 #define lpfc_reg_fcfi_type_match2_WORD	word6
2543 #define lpfc_reg_fcfi_type_mask2_SHIFT	16
2544 #define lpfc_reg_fcfi_type_mask2_MASK	0x000000FF
2545 #define lpfc_reg_fcfi_type_mask2_WORD	word6
2546 #define lpfc_reg_fcfi_rctl_match2_SHIFT	8
2547 #define lpfc_reg_fcfi_rctl_match2_MASK	0x000000FF
2548 #define lpfc_reg_fcfi_rctl_match2_WORD	word6
2549 #define lpfc_reg_fcfi_rctl_mask2_SHIFT	0
2550 #define lpfc_reg_fcfi_rctl_mask2_MASK	0x000000FF
2551 #define lpfc_reg_fcfi_rctl_mask2_WORD	word6
2552 	uint32_t word7;
2553 #define lpfc_reg_fcfi_type_match3_SHIFT	24
2554 #define lpfc_reg_fcfi_type_match3_MASK	0x000000FF
2555 #define lpfc_reg_fcfi_type_match3_WORD	word7
2556 #define lpfc_reg_fcfi_type_mask3_SHIFT	16
2557 #define lpfc_reg_fcfi_type_mask3_MASK	0x000000FF
2558 #define lpfc_reg_fcfi_type_mask3_WORD	word7
2559 #define lpfc_reg_fcfi_rctl_match3_SHIFT	8
2560 #define lpfc_reg_fcfi_rctl_match3_MASK	0x000000FF
2561 #define lpfc_reg_fcfi_rctl_match3_WORD	word7
2562 #define lpfc_reg_fcfi_rctl_mask3_SHIFT	0
2563 #define lpfc_reg_fcfi_rctl_mask3_MASK	0x000000FF
2564 #define lpfc_reg_fcfi_rctl_mask3_WORD	word7
2565 	uint32_t word8;
2566 #define lpfc_reg_fcfi_mam_SHIFT		13
2567 #define lpfc_reg_fcfi_mam_MASK		0x00000003
2568 #define lpfc_reg_fcfi_mam_WORD		word8
2569 #define LPFC_MAM_BOTH		0	/* Both SPMA and FPMA */
2570 #define LPFC_MAM_SPMA		1	/* Server Provided MAC Address */
2571 #define LPFC_MAM_FPMA		2	/* Fabric Provided MAC Address */
2572 #define lpfc_reg_fcfi_vv_SHIFT		12
2573 #define lpfc_reg_fcfi_vv_MASK		0x00000001
2574 #define lpfc_reg_fcfi_vv_WORD		word8
2575 #define lpfc_reg_fcfi_vlan_tag_SHIFT	0
2576 #define lpfc_reg_fcfi_vlan_tag_MASK	0x00000FFF
2577 #define lpfc_reg_fcfi_vlan_tag_WORD	word8
2578 };
2579 
2580 struct lpfc_mbx_reg_fcfi_mrq {
2581 	uint32_t word1;
2582 #define lpfc_reg_fcfi_mrq_info_index_SHIFT	0
2583 #define lpfc_reg_fcfi_mrq_info_index_MASK	0x0000FFFF
2584 #define lpfc_reg_fcfi_mrq_info_index_WORD	word1
2585 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT		16
2586 #define lpfc_reg_fcfi_mrq_fcfi_MASK		0x0000FFFF
2587 #define lpfc_reg_fcfi_mrq_fcfi_WORD		word1
2588 	uint32_t word2;
2589 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT		0
2590 #define lpfc_reg_fcfi_mrq_rq_id1_MASK		0x0000FFFF
2591 #define lpfc_reg_fcfi_mrq_rq_id1_WORD		word2
2592 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT		16
2593 #define lpfc_reg_fcfi_mrq_rq_id0_MASK		0x0000FFFF
2594 #define lpfc_reg_fcfi_mrq_rq_id0_WORD		word2
2595 	uint32_t word3;
2596 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT		0
2597 #define lpfc_reg_fcfi_mrq_rq_id3_MASK		0x0000FFFF
2598 #define lpfc_reg_fcfi_mrq_rq_id3_WORD		word3
2599 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT		16
2600 #define lpfc_reg_fcfi_mrq_rq_id2_MASK		0x0000FFFF
2601 #define lpfc_reg_fcfi_mrq_rq_id2_WORD		word3
2602 	uint32_t word4;
2603 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT	24
2604 #define lpfc_reg_fcfi_mrq_type_match0_MASK	0x000000FF
2605 #define lpfc_reg_fcfi_mrq_type_match0_WORD	word4
2606 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT	16
2607 #define lpfc_reg_fcfi_mrq_type_mask0_MASK	0x000000FF
2608 #define lpfc_reg_fcfi_mrq_type_mask0_WORD	word4
2609 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT	8
2610 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK	0x000000FF
2611 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD	word4
2612 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT	0
2613 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK	0x000000FF
2614 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD	word4
2615 	uint32_t word5;
2616 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT	24
2617 #define lpfc_reg_fcfi_mrq_type_match1_MASK	0x000000FF
2618 #define lpfc_reg_fcfi_mrq_type_match1_WORD	word5
2619 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT	16
2620 #define lpfc_reg_fcfi_mrq_type_mask1_MASK	0x000000FF
2621 #define lpfc_reg_fcfi_mrq_type_mask1_WORD	word5
2622 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT	8
2623 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK	0x000000FF
2624 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD	word5
2625 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT	0
2626 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK	0x000000FF
2627 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD	word5
2628 	uint32_t word6;
2629 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT	24
2630 #define lpfc_reg_fcfi_mrq_type_match2_MASK	0x000000FF
2631 #define lpfc_reg_fcfi_mrq_type_match2_WORD	word6
2632 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT	16
2633 #define lpfc_reg_fcfi_mrq_type_mask2_MASK	0x000000FF
2634 #define lpfc_reg_fcfi_mrq_type_mask2_WORD	word6
2635 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT	8
2636 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK	0x000000FF
2637 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD	word6
2638 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT	0
2639 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK	0x000000FF
2640 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD	word6
2641 	uint32_t word7;
2642 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT	24
2643 #define lpfc_reg_fcfi_mrq_type_match3_MASK	0x000000FF
2644 #define lpfc_reg_fcfi_mrq_type_match3_WORD	word7
2645 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT	16
2646 #define lpfc_reg_fcfi_mrq_type_mask3_MASK	0x000000FF
2647 #define lpfc_reg_fcfi_mrq_type_mask3_WORD	word7
2648 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT	8
2649 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK	0x000000FF
2650 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD	word7
2651 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT	0
2652 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK	0x000000FF
2653 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD	word7
2654 	uint32_t word8;
2655 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT		31
2656 #define lpfc_reg_fcfi_mrq_ptc7_MASK		0x00000001
2657 #define lpfc_reg_fcfi_mrq_ptc7_WORD		word8
2658 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT		30
2659 #define lpfc_reg_fcfi_mrq_ptc6_MASK		0x00000001
2660 #define lpfc_reg_fcfi_mrq_ptc6_WORD		word8
2661 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT		29
2662 #define lpfc_reg_fcfi_mrq_ptc5_MASK		0x00000001
2663 #define lpfc_reg_fcfi_mrq_ptc5_WORD		word8
2664 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT		28
2665 #define lpfc_reg_fcfi_mrq_ptc4_MASK		0x00000001
2666 #define lpfc_reg_fcfi_mrq_ptc4_WORD		word8
2667 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT		27
2668 #define lpfc_reg_fcfi_mrq_ptc3_MASK		0x00000001
2669 #define lpfc_reg_fcfi_mrq_ptc3_WORD		word8
2670 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT		26
2671 #define lpfc_reg_fcfi_mrq_ptc2_MASK		0x00000001
2672 #define lpfc_reg_fcfi_mrq_ptc2_WORD		word8
2673 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT		25
2674 #define lpfc_reg_fcfi_mrq_ptc1_MASK		0x00000001
2675 #define lpfc_reg_fcfi_mrq_ptc1_WORD		word8
2676 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT		24
2677 #define lpfc_reg_fcfi_mrq_ptc0_MASK		0x00000001
2678 #define lpfc_reg_fcfi_mrq_ptc0_WORD		word8
2679 #define lpfc_reg_fcfi_mrq_pt7_SHIFT		23
2680 #define lpfc_reg_fcfi_mrq_pt7_MASK		0x00000001
2681 #define lpfc_reg_fcfi_mrq_pt7_WORD		word8
2682 #define lpfc_reg_fcfi_mrq_pt6_SHIFT		22
2683 #define lpfc_reg_fcfi_mrq_pt6_MASK		0x00000001
2684 #define lpfc_reg_fcfi_mrq_pt6_WORD		word8
2685 #define lpfc_reg_fcfi_mrq_pt5_SHIFT		21
2686 #define lpfc_reg_fcfi_mrq_pt5_MASK		0x00000001
2687 #define lpfc_reg_fcfi_mrq_pt5_WORD		word8
2688 #define lpfc_reg_fcfi_mrq_pt4_SHIFT		20
2689 #define lpfc_reg_fcfi_mrq_pt4_MASK		0x00000001
2690 #define lpfc_reg_fcfi_mrq_pt4_WORD		word8
2691 #define lpfc_reg_fcfi_mrq_pt3_SHIFT		19
2692 #define lpfc_reg_fcfi_mrq_pt3_MASK		0x00000001
2693 #define lpfc_reg_fcfi_mrq_pt3_WORD		word8
2694 #define lpfc_reg_fcfi_mrq_pt2_SHIFT		18
2695 #define lpfc_reg_fcfi_mrq_pt2_MASK		0x00000001
2696 #define lpfc_reg_fcfi_mrq_pt2_WORD		word8
2697 #define lpfc_reg_fcfi_mrq_pt1_SHIFT		17
2698 #define lpfc_reg_fcfi_mrq_pt1_MASK		0x00000001
2699 #define lpfc_reg_fcfi_mrq_pt1_WORD		word8
2700 #define lpfc_reg_fcfi_mrq_pt0_SHIFT		16
2701 #define lpfc_reg_fcfi_mrq_pt0_MASK		0x00000001
2702 #define lpfc_reg_fcfi_mrq_pt0_WORD		word8
2703 #define lpfc_reg_fcfi_mrq_xmv_SHIFT		15
2704 #define lpfc_reg_fcfi_mrq_xmv_MASK		0x00000001
2705 #define lpfc_reg_fcfi_mrq_xmv_WORD		word8
2706 #define lpfc_reg_fcfi_mrq_mode_SHIFT		13
2707 #define lpfc_reg_fcfi_mrq_mode_MASK		0x00000001
2708 #define lpfc_reg_fcfi_mrq_mode_WORD		word8
2709 #define lpfc_reg_fcfi_mrq_vv_SHIFT		12
2710 #define lpfc_reg_fcfi_mrq_vv_MASK		0x00000001
2711 #define lpfc_reg_fcfi_mrq_vv_WORD		word8
2712 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT	0
2713 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK		0x00000FFF
2714 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD		word8
2715 	uint32_t word9;
2716 #define lpfc_reg_fcfi_mrq_policy_SHIFT		12
2717 #define lpfc_reg_fcfi_mrq_policy_MASK		0x0000000F
2718 #define lpfc_reg_fcfi_mrq_policy_WORD		word9
2719 #define lpfc_reg_fcfi_mrq_filter_SHIFT		8
2720 #define lpfc_reg_fcfi_mrq_filter_MASK		0x0000000F
2721 #define lpfc_reg_fcfi_mrq_filter_WORD		word9
2722 #define lpfc_reg_fcfi_mrq_npairs_SHIFT		0
2723 #define lpfc_reg_fcfi_mrq_npairs_MASK		0x000000FF
2724 #define lpfc_reg_fcfi_mrq_npairs_WORD		word9
2725 	uint32_t word10;
2726 	uint32_t word11;
2727 	uint32_t word12;
2728 	uint32_t word13;
2729 	uint32_t word14;
2730 	uint32_t word15;
2731 	uint32_t word16;
2732 };
2733 
2734 struct lpfc_mbx_unreg_fcfi {
2735 	uint32_t word1_rsv;
2736 	uint32_t word2;
2737 #define lpfc_unreg_fcfi_SHIFT		0
2738 #define lpfc_unreg_fcfi_MASK		0x0000FFFF
2739 #define lpfc_unreg_fcfi_WORD		word2
2740 };
2741 
2742 struct lpfc_mbx_read_rev {
2743 	uint32_t word1;
2744 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT  		16
2745 #define lpfc_mbx_rd_rev_sli_lvl_MASK   		0x0000000F
2746 #define lpfc_mbx_rd_rev_sli_lvl_WORD   		word1
2747 #define lpfc_mbx_rd_rev_fcoe_SHIFT		20
2748 #define lpfc_mbx_rd_rev_fcoe_MASK		0x00000001
2749 #define lpfc_mbx_rd_rev_fcoe_WORD		word1
2750 #define lpfc_mbx_rd_rev_cee_ver_SHIFT		21
2751 #define lpfc_mbx_rd_rev_cee_ver_MASK		0x00000003
2752 #define lpfc_mbx_rd_rev_cee_ver_WORD		word1
2753 #define LPFC_PREDCBX_CEE_MODE	0
2754 #define LPFC_DCBX_CEE_MODE	1
2755 #define lpfc_mbx_rd_rev_vpd_SHIFT		29
2756 #define lpfc_mbx_rd_rev_vpd_MASK		0x00000001
2757 #define lpfc_mbx_rd_rev_vpd_WORD		word1
2758 	uint32_t first_hw_rev;
2759 #define LPFC_G7_ASIC_1				0xd
2760 	uint32_t second_hw_rev;
2761 	uint32_t word4_rsvd;
2762 	uint32_t third_hw_rev;
2763 	uint32_t word6;
2764 #define lpfc_mbx_rd_rev_fcph_low_SHIFT		0
2765 #define lpfc_mbx_rd_rev_fcph_low_MASK		0x000000FF
2766 #define lpfc_mbx_rd_rev_fcph_low_WORD		word6
2767 #define lpfc_mbx_rd_rev_fcph_high_SHIFT		8
2768 #define lpfc_mbx_rd_rev_fcph_high_MASK		0x000000FF
2769 #define lpfc_mbx_rd_rev_fcph_high_WORD		word6
2770 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT	16
2771 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK	0x000000FF
2772 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD	word6
2773 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT	24
2774 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK	0x000000FF
2775 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD	word6
2776 	uint32_t word7_rsvd;
2777 	uint32_t fw_id_rev;
2778 	uint8_t  fw_name[16];
2779 	uint32_t ulp_fw_id_rev;
2780 	uint8_t  ulp_fw_name[16];
2781 	uint32_t word18_47_rsvd[30];
2782 	uint32_t word48;
2783 #define lpfc_mbx_rd_rev_avail_len_SHIFT		0
2784 #define lpfc_mbx_rd_rev_avail_len_MASK		0x00FFFFFF
2785 #define lpfc_mbx_rd_rev_avail_len_WORD		word48
2786 	uint32_t vpd_paddr_low;
2787 	uint32_t vpd_paddr_high;
2788 	uint32_t avail_vpd_len;
2789 	uint32_t rsvd_52_63[12];
2790 };
2791 
2792 struct lpfc_mbx_read_config {
2793 	uint32_t word1;
2794 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT	31
2795 #define lpfc_mbx_rd_conf_extnts_inuse_MASK	0x00000001
2796 #define lpfc_mbx_rd_conf_extnts_inuse_WORD	word1
2797 	uint32_t word2;
2798 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT		0
2799 #define lpfc_mbx_rd_conf_lnk_numb_MASK		0x0000003F
2800 #define lpfc_mbx_rd_conf_lnk_numb_WORD		word2
2801 #define lpfc_mbx_rd_conf_lnk_type_SHIFT		6
2802 #define lpfc_mbx_rd_conf_lnk_type_MASK		0x00000003
2803 #define lpfc_mbx_rd_conf_lnk_type_WORD		word2
2804 #define LPFC_LNK_TYPE_GE	0
2805 #define LPFC_LNK_TYPE_FC	1
2806 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT		8
2807 #define lpfc_mbx_rd_conf_lnk_ldv_MASK		0x00000001
2808 #define lpfc_mbx_rd_conf_lnk_ldv_WORD		word2
2809 #define lpfc_mbx_rd_conf_trunk_SHIFT		12
2810 #define lpfc_mbx_rd_conf_trunk_MASK		0x0000000F
2811 #define lpfc_mbx_rd_conf_trunk_WORD		word2
2812 #define lpfc_mbx_rd_conf_topology_SHIFT		24
2813 #define lpfc_mbx_rd_conf_topology_MASK		0x000000FF
2814 #define lpfc_mbx_rd_conf_topology_WORD		word2
2815 	uint32_t rsvd_3;
2816 	uint32_t word4;
2817 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT		0
2818 #define lpfc_mbx_rd_conf_e_d_tov_MASK		0x0000FFFF
2819 #define lpfc_mbx_rd_conf_e_d_tov_WORD		word4
2820 	uint32_t rsvd_5;
2821 	uint32_t word6;
2822 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT		0
2823 #define lpfc_mbx_rd_conf_r_a_tov_MASK		0x0000FFFF
2824 #define lpfc_mbx_rd_conf_r_a_tov_WORD		word6
2825 #define lpfc_mbx_rd_conf_link_speed_SHIFT	16
2826 #define lpfc_mbx_rd_conf_link_speed_MASK	0x0000FFFF
2827 #define lpfc_mbx_rd_conf_link_speed_WORD	word6
2828 	uint32_t rsvd_7;
2829 	uint32_t word8;
2830 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT	0
2831 #define lpfc_mbx_rd_conf_bbscn_min_MASK		0x0000000F
2832 #define lpfc_mbx_rd_conf_bbscn_min_WORD		word8
2833 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT	4
2834 #define lpfc_mbx_rd_conf_bbscn_max_MASK		0x0000000F
2835 #define lpfc_mbx_rd_conf_bbscn_max_WORD		word8
2836 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT	8
2837 #define lpfc_mbx_rd_conf_bbscn_def_MASK		0x0000000F
2838 #define lpfc_mbx_rd_conf_bbscn_def_WORD		word8
2839 	uint32_t word9;
2840 #define lpfc_mbx_rd_conf_lmt_SHIFT		0
2841 #define lpfc_mbx_rd_conf_lmt_MASK		0x0000FFFF
2842 #define lpfc_mbx_rd_conf_lmt_WORD		word9
2843 	uint32_t rsvd_10;
2844 	uint32_t rsvd_11;
2845 	uint32_t word12;
2846 #define lpfc_mbx_rd_conf_xri_base_SHIFT		0
2847 #define lpfc_mbx_rd_conf_xri_base_MASK		0x0000FFFF
2848 #define lpfc_mbx_rd_conf_xri_base_WORD		word12
2849 #define lpfc_mbx_rd_conf_xri_count_SHIFT	16
2850 #define lpfc_mbx_rd_conf_xri_count_MASK		0x0000FFFF
2851 #define lpfc_mbx_rd_conf_xri_count_WORD		word12
2852 	uint32_t word13;
2853 #define lpfc_mbx_rd_conf_rpi_base_SHIFT		0
2854 #define lpfc_mbx_rd_conf_rpi_base_MASK		0x0000FFFF
2855 #define lpfc_mbx_rd_conf_rpi_base_WORD		word13
2856 #define lpfc_mbx_rd_conf_rpi_count_SHIFT	16
2857 #define lpfc_mbx_rd_conf_rpi_count_MASK		0x0000FFFF
2858 #define lpfc_mbx_rd_conf_rpi_count_WORD		word13
2859 	uint32_t word14;
2860 #define lpfc_mbx_rd_conf_vpi_base_SHIFT		0
2861 #define lpfc_mbx_rd_conf_vpi_base_MASK		0x0000FFFF
2862 #define lpfc_mbx_rd_conf_vpi_base_WORD		word14
2863 #define lpfc_mbx_rd_conf_vpi_count_SHIFT	16
2864 #define lpfc_mbx_rd_conf_vpi_count_MASK		0x0000FFFF
2865 #define lpfc_mbx_rd_conf_vpi_count_WORD		word14
2866 	uint32_t word15;
2867 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
2868 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
2869 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
2870 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
2871 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
2872 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
2873 	uint32_t word16;
2874 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT	16
2875 #define lpfc_mbx_rd_conf_fcfi_count_MASK	0x0000FFFF
2876 #define lpfc_mbx_rd_conf_fcfi_count_WORD	word16
2877 	uint32_t word17;
2878 #define lpfc_mbx_rd_conf_rq_count_SHIFT		0
2879 #define lpfc_mbx_rd_conf_rq_count_MASK		0x0000FFFF
2880 #define lpfc_mbx_rd_conf_rq_count_WORD		word17
2881 #define lpfc_mbx_rd_conf_eq_count_SHIFT		16
2882 #define lpfc_mbx_rd_conf_eq_count_MASK		0x0000FFFF
2883 #define lpfc_mbx_rd_conf_eq_count_WORD		word17
2884 	uint32_t word18;
2885 #define lpfc_mbx_rd_conf_wq_count_SHIFT		0
2886 #define lpfc_mbx_rd_conf_wq_count_MASK		0x0000FFFF
2887 #define lpfc_mbx_rd_conf_wq_count_WORD		word18
2888 #define lpfc_mbx_rd_conf_cq_count_SHIFT		16
2889 #define lpfc_mbx_rd_conf_cq_count_MASK		0x0000FFFF
2890 #define lpfc_mbx_rd_conf_cq_count_WORD		word18
2891 };
2892 
2893 struct lpfc_mbx_request_features {
2894 	uint32_t word1;
2895 #define lpfc_mbx_rq_ftr_qry_SHIFT		0
2896 #define lpfc_mbx_rq_ftr_qry_MASK		0x00000001
2897 #define lpfc_mbx_rq_ftr_qry_WORD		word1
2898 	uint32_t word2;
2899 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT		0
2900 #define lpfc_mbx_rq_ftr_rq_iaab_MASK		0x00000001
2901 #define lpfc_mbx_rq_ftr_rq_iaab_WORD		word2
2902 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT		1
2903 #define lpfc_mbx_rq_ftr_rq_npiv_MASK		0x00000001
2904 #define lpfc_mbx_rq_ftr_rq_npiv_WORD		word2
2905 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT		2
2906 #define lpfc_mbx_rq_ftr_rq_dif_MASK		0x00000001
2907 #define lpfc_mbx_rq_ftr_rq_dif_WORD		word2
2908 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT		3
2909 #define lpfc_mbx_rq_ftr_rq_vf_MASK		0x00000001
2910 #define lpfc_mbx_rq_ftr_rq_vf_WORD		word2
2911 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT		4
2912 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK		0x00000001
2913 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD		word2
2914 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT		5
2915 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK		0x00000001
2916 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD		word2
2917 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT		6
2918 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK		0x00000001
2919 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD		word2
2920 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT		7
2921 #define lpfc_mbx_rq_ftr_rq_ifip_MASK		0x00000001
2922 #define lpfc_mbx_rq_ftr_rq_ifip_WORD		word2
2923 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT		9
2924 #define lpfc_mbx_rq_ftr_rq_iaar_MASK		0x00000001
2925 #define lpfc_mbx_rq_ftr_rq_iaar_WORD		word2
2926 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT		11
2927 #define lpfc_mbx_rq_ftr_rq_perfh_MASK		0x00000001
2928 #define lpfc_mbx_rq_ftr_rq_perfh_WORD		word2
2929 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT		16
2930 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK		0x00000001
2931 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD		word2
2932 	uint32_t word3;
2933 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT		0
2934 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK		0x00000001
2935 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD		word3
2936 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT		1
2937 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK		0x00000001
2938 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD		word3
2939 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT		2
2940 #define lpfc_mbx_rq_ftr_rsp_dif_MASK		0x00000001
2941 #define lpfc_mbx_rq_ftr_rsp_dif_WORD		word3
2942 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT		3
2943 #define lpfc_mbx_rq_ftr_rsp_vf__MASK		0x00000001
2944 #define lpfc_mbx_rq_ftr_rsp_vf_WORD		word3
2945 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT		4
2946 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK		0x00000001
2947 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD		word3
2948 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT		5
2949 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK		0x00000001
2950 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD		word3
2951 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT		6
2952 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK		0x00000001
2953 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD		word3
2954 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT		7
2955 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK		0x00000001
2956 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD		word3
2957 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT		11
2958 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK		0x00000001
2959 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD		word3
2960 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT		16
2961 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK		0x00000001
2962 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD		word3
2963 };
2964 
2965 struct lpfc_mbx_supp_pages {
2966 	uint32_t word1;
2967 #define qs_SHIFT 				0
2968 #define qs_MASK					0x00000001
2969 #define qs_WORD					word1
2970 #define wr_SHIFT				1
2971 #define wr_MASK 				0x00000001
2972 #define wr_WORD					word1
2973 #define pf_SHIFT				8
2974 #define pf_MASK					0x000000ff
2975 #define pf_WORD					word1
2976 #define cpn_SHIFT				16
2977 #define cpn_MASK				0x000000ff
2978 #define cpn_WORD				word1
2979 	uint32_t word2;
2980 #define list_offset_SHIFT 			0
2981 #define list_offset_MASK			0x000000ff
2982 #define list_offset_WORD			word2
2983 #define next_offset_SHIFT			8
2984 #define next_offset_MASK			0x000000ff
2985 #define next_offset_WORD			word2
2986 #define elem_cnt_SHIFT				16
2987 #define elem_cnt_MASK				0x000000ff
2988 #define elem_cnt_WORD				word2
2989 	uint32_t word3;
2990 #define pn_0_SHIFT				24
2991 #define pn_0_MASK  				0x000000ff
2992 #define pn_0_WORD				word3
2993 #define pn_1_SHIFT				16
2994 #define pn_1_MASK				0x000000ff
2995 #define pn_1_WORD				word3
2996 #define pn_2_SHIFT				8
2997 #define pn_2_MASK				0x000000ff
2998 #define pn_2_WORD				word3
2999 #define pn_3_SHIFT				0
3000 #define pn_3_MASK				0x000000ff
3001 #define pn_3_WORD				word3
3002 	uint32_t word4;
3003 #define pn_4_SHIFT				24
3004 #define pn_4_MASK				0x000000ff
3005 #define pn_4_WORD				word4
3006 #define pn_5_SHIFT				16
3007 #define pn_5_MASK				0x000000ff
3008 #define pn_5_WORD				word4
3009 #define pn_6_SHIFT				8
3010 #define pn_6_MASK				0x000000ff
3011 #define pn_6_WORD				word4
3012 #define pn_7_SHIFT				0
3013 #define pn_7_MASK				0x000000ff
3014 #define pn_7_WORD				word4
3015 	uint32_t rsvd[27];
3016 #define LPFC_SUPP_PAGES			0
3017 #define LPFC_BLOCK_GUARD_PROFILES	1
3018 #define LPFC_SLI4_PARAMETERS		2
3019 };
3020 
3021 struct lpfc_mbx_memory_dump_type3 {
3022 	uint32_t word1;
3023 #define lpfc_mbx_memory_dump_type3_type_SHIFT    0
3024 #define lpfc_mbx_memory_dump_type3_type_MASK     0x0000000f
3025 #define lpfc_mbx_memory_dump_type3_type_WORD     word1
3026 #define lpfc_mbx_memory_dump_type3_link_SHIFT    24
3027 #define lpfc_mbx_memory_dump_type3_link_MASK     0x000000ff
3028 #define lpfc_mbx_memory_dump_type3_link_WORD     word1
3029 	uint32_t word2;
3030 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT  0
3031 #define lpfc_mbx_memory_dump_type3_page_no_MASK   0x0000ffff
3032 #define lpfc_mbx_memory_dump_type3_page_no_WORD   word2
3033 #define lpfc_mbx_memory_dump_type3_offset_SHIFT   16
3034 #define lpfc_mbx_memory_dump_type3_offset_MASK    0x0000ffff
3035 #define lpfc_mbx_memory_dump_type3_offset_WORD    word2
3036 	uint32_t word3;
3037 #define lpfc_mbx_memory_dump_type3_length_SHIFT  0
3038 #define lpfc_mbx_memory_dump_type3_length_MASK   0x00ffffff
3039 #define lpfc_mbx_memory_dump_type3_length_WORD   word3
3040 	uint32_t addr_lo;
3041 	uint32_t addr_hi;
3042 	uint32_t return_len;
3043 };
3044 
3045 #define DMP_PAGE_A0             0xa0
3046 #define DMP_PAGE_A2             0xa2
3047 #define DMP_SFF_PAGE_A0_SIZE	256
3048 #define DMP_SFF_PAGE_A2_SIZE	256
3049 
3050 #define SFP_WAVELENGTH_LC1310	1310
3051 #define SFP_WAVELENGTH_LL1550	1550
3052 
3053 
3054 /*
3055  *  * SFF-8472 TABLE 3.4
3056  *   */
3057 #define  SFF_PG0_CONNECTOR_UNKNOWN    0x00   /* Unknown  */
3058 #define  SFF_PG0_CONNECTOR_SC         0x01   /* SC       */
3059 #define  SFF_PG0_CONNECTOR_FC_COPPER1 0x02   /* FC style 1 copper connector */
3060 #define  SFF_PG0_CONNECTOR_FC_COPPER2 0x03   /* FC style 2 copper connector */
3061 #define  SFF_PG0_CONNECTOR_BNC        0x04   /* BNC / TNC */
3062 #define  SFF_PG0_CONNECTOR__FC_COAX   0x05   /* FC coaxial headers */
3063 #define  SFF_PG0_CONNECTOR_FIBERJACK  0x06   /* FiberJack */
3064 #define  SFF_PG0_CONNECTOR_LC         0x07   /* LC        */
3065 #define  SFF_PG0_CONNECTOR_MT         0x08   /* MT - RJ   */
3066 #define  SFF_PG0_CONNECTOR_MU         0x09   /* MU        */
3067 #define  SFF_PG0_CONNECTOR_SF         0x0A   /* SG        */
3068 #define  SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3069 #define  SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3070 #define  SFF_PG0_CONNECTOR_HSSDC_II   0x20   /* HSSDC II */
3071 #define  SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3072 #define  SFF_PG0_CONNECTOR_RJ45       0x22  /* RJ45 */
3073 
3074 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
3075 
3076 #define SSF_IDENTIFIER			0
3077 #define SSF_EXT_IDENTIFIER		1
3078 #define SSF_CONNECTOR			2
3079 #define SSF_TRANSCEIVER_CODE_B0		3
3080 #define SSF_TRANSCEIVER_CODE_B1		4
3081 #define SSF_TRANSCEIVER_CODE_B2		5
3082 #define SSF_TRANSCEIVER_CODE_B3		6
3083 #define SSF_TRANSCEIVER_CODE_B4		7
3084 #define SSF_TRANSCEIVER_CODE_B5		8
3085 #define SSF_TRANSCEIVER_CODE_B6		9
3086 #define SSF_TRANSCEIVER_CODE_B7		10
3087 #define SSF_ENCODING			11
3088 #define SSF_BR_NOMINAL			12
3089 #define SSF_RATE_IDENTIFIER		13
3090 #define SSF_LENGTH_9UM_KM		14
3091 #define SSF_LENGTH_9UM			15
3092 #define SSF_LENGTH_50UM_OM2		16
3093 #define SSF_LENGTH_62UM_OM1		17
3094 #define SFF_LENGTH_COPPER		18
3095 #define SSF_LENGTH_50UM_OM3		19
3096 #define SSF_VENDOR_NAME			20
3097 #define SSF_VENDOR_OUI			36
3098 #define SSF_VENDOR_PN			40
3099 #define SSF_VENDOR_REV			56
3100 #define SSF_WAVELENGTH_B1		60
3101 #define SSF_WAVELENGTH_B0		61
3102 #define SSF_CC_BASE			63
3103 #define SSF_OPTIONS_B1			64
3104 #define SSF_OPTIONS_B0			65
3105 #define SSF_BR_MAX			66
3106 #define SSF_BR_MIN			67
3107 #define SSF_VENDOR_SN			68
3108 #define SSF_DATE_CODE			84
3109 #define SSF_MONITORING_TYPEDIAGNOSTIC	92
3110 #define SSF_ENHANCED_OPTIONS		93
3111 #define SFF_8472_COMPLIANCE		94
3112 #define SSF_CC_EXT			95
3113 #define SSF_A0_VENDOR_SPECIFIC		96
3114 
3115 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
3116 
3117 #define SSF_TEMP_HIGH_ALARM		0
3118 #define SSF_TEMP_LOW_ALARM		2
3119 #define SSF_TEMP_HIGH_WARNING		4
3120 #define SSF_TEMP_LOW_WARNING		6
3121 #define SSF_VOLTAGE_HIGH_ALARM		8
3122 #define SSF_VOLTAGE_LOW_ALARM		10
3123 #define SSF_VOLTAGE_HIGH_WARNING	12
3124 #define SSF_VOLTAGE_LOW_WARNING		14
3125 #define SSF_BIAS_HIGH_ALARM		16
3126 #define SSF_BIAS_LOW_ALARM		18
3127 #define SSF_BIAS_HIGH_WARNING		20
3128 #define SSF_BIAS_LOW_WARNING		22
3129 #define SSF_TXPOWER_HIGH_ALARM		24
3130 #define SSF_TXPOWER_LOW_ALARM		26
3131 #define SSF_TXPOWER_HIGH_WARNING	28
3132 #define SSF_TXPOWER_LOW_WARNING		30
3133 #define SSF_RXPOWER_HIGH_ALARM		32
3134 #define SSF_RXPOWER_LOW_ALARM		34
3135 #define SSF_RXPOWER_HIGH_WARNING	36
3136 #define SSF_RXPOWER_LOW_WARNING		38
3137 #define SSF_EXT_CAL_CONSTANTS		56
3138 #define SSF_CC_DMI			95
3139 #define SFF_TEMPERATURE_B1		96
3140 #define SFF_TEMPERATURE_B0		97
3141 #define SFF_VCC_B1			98
3142 #define SFF_VCC_B0			99
3143 #define SFF_TX_BIAS_CURRENT_B1		100
3144 #define SFF_TX_BIAS_CURRENT_B0		101
3145 #define SFF_TXPOWER_B1			102
3146 #define SFF_TXPOWER_B0			103
3147 #define SFF_RXPOWER_B1			104
3148 #define SFF_RXPOWER_B0			105
3149 #define SSF_STATUS_CONTROL		110
3150 #define SSF_ALARM_FLAGS			112
3151 #define SSF_WARNING_FLAGS		116
3152 #define SSF_EXT_TATUS_CONTROL_B1	118
3153 #define SSF_EXT_TATUS_CONTROL_B0	119
3154 #define SSF_A2_VENDOR_SPECIFIC		120
3155 #define SSF_USER_EEPROM			128
3156 #define SSF_VENDOR_CONTROL		148
3157 
3158 
3159 /*
3160  * Tranceiver codes Fibre Channel SFF-8472
3161  * Table 3.5.
3162  */
3163 
3164 struct sff_trasnceiver_codes_byte0 {
3165 	uint8_t inifiband:4;
3166 	uint8_t teng_ethernet:4;
3167 };
3168 
3169 struct sff_trasnceiver_codes_byte1 {
3170 	uint8_t  sonet:6;
3171 	uint8_t  escon:2;
3172 };
3173 
3174 struct sff_trasnceiver_codes_byte2 {
3175 	uint8_t  soNet:8;
3176 };
3177 
3178 struct sff_trasnceiver_codes_byte3 {
3179 	uint8_t ethernet:8;
3180 };
3181 
3182 struct sff_trasnceiver_codes_byte4 {
3183 	uint8_t fc_el_lo:1;
3184 	uint8_t fc_lw_laser:1;
3185 	uint8_t fc_sw_laser:1;
3186 	uint8_t fc_md_distance:1;
3187 	uint8_t fc_lg_distance:1;
3188 	uint8_t fc_int_distance:1;
3189 	uint8_t fc_short_distance:1;
3190 	uint8_t fc_vld_distance:1;
3191 };
3192 
3193 struct sff_trasnceiver_codes_byte5 {
3194 	uint8_t reserved1:1;
3195 	uint8_t reserved2:1;
3196 	uint8_t fc_sfp_active:1;  /* Active cable   */
3197 	uint8_t fc_sfp_passive:1; /* Passive cable  */
3198 	uint8_t fc_lw_laser:1;     /* Longwave laser */
3199 	uint8_t fc_sw_laser_sl:1;
3200 	uint8_t fc_sw_laser_sn:1;
3201 	uint8_t fc_el_hi:1;        /* Electrical enclosure high bit */
3202 };
3203 
3204 struct sff_trasnceiver_codes_byte6 {
3205 	uint8_t fc_tm_sm:1;      /* Single Mode */
3206 	uint8_t reserved:1;
3207 	uint8_t fc_tm_m6:1;       /* Multimode, 62.5um (M6) */
3208 	uint8_t fc_tm_tv:1;      /* Video Coax (TV) */
3209 	uint8_t fc_tm_mi:1;      /* Miniature Coax (MI) */
3210 	uint8_t fc_tm_tp:1;      /* Twisted Pair (TP) */
3211 	uint8_t fc_tm_tw:1;      /* Twin Axial Pair  */
3212 };
3213 
3214 struct sff_trasnceiver_codes_byte7 {
3215 	uint8_t fc_sp_100MB:1;   /*  100 MB/sec */
3216 	uint8_t reserve:1;
3217 	uint8_t fc_sp_200mb:1;   /*  200 MB/sec */
3218 	uint8_t fc_sp_3200MB:1;  /* 3200 MB/sec */
3219 	uint8_t fc_sp_400MB:1;   /*  400 MB/sec */
3220 	uint8_t fc_sp_1600MB:1;  /* 1600 MB/sec */
3221 	uint8_t fc_sp_800MB:1;   /*  800 MB/sec */
3222 	uint8_t fc_sp_1200MB:1;  /* 1200 MB/sec */
3223 };
3224 
3225 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
3226 struct user_eeprom {
3227 	uint8_t vendor_name[16];
3228 	uint8_t vendor_oui[3];
3229 	uint8_t vendor_pn[816];
3230 	uint8_t vendor_rev[4];
3231 	uint8_t vendor_sn[16];
3232 	uint8_t datecode[6];
3233 	uint8_t lot_code[2];
3234 	uint8_t reserved191[57];
3235 };
3236 
3237 struct lpfc_mbx_pc_sli4_params {
3238 	uint32_t word1;
3239 #define qs_SHIFT				0
3240 #define qs_MASK					0x00000001
3241 #define qs_WORD					word1
3242 #define wr_SHIFT				1
3243 #define wr_MASK					0x00000001
3244 #define wr_WORD					word1
3245 #define pf_SHIFT				8
3246 #define pf_MASK					0x000000ff
3247 #define pf_WORD					word1
3248 #define cpn_SHIFT				16
3249 #define cpn_MASK				0x000000ff
3250 #define cpn_WORD				word1
3251 	uint32_t word2;
3252 #define if_type_SHIFT				0
3253 #define if_type_MASK				0x00000007
3254 #define if_type_WORD				word2
3255 #define sli_rev_SHIFT				4
3256 #define sli_rev_MASK				0x0000000f
3257 #define sli_rev_WORD				word2
3258 #define sli_family_SHIFT			8
3259 #define sli_family_MASK				0x000000ff
3260 #define sli_family_WORD				word2
3261 #define featurelevel_1_SHIFT			16
3262 #define featurelevel_1_MASK			0x000000ff
3263 #define featurelevel_1_WORD			word2
3264 #define featurelevel_2_SHIFT			24
3265 #define featurelevel_2_MASK			0x0000001f
3266 #define featurelevel_2_WORD			word2
3267 	uint32_t word3;
3268 #define fcoe_SHIFT 				0
3269 #define fcoe_MASK				0x00000001
3270 #define fcoe_WORD				word3
3271 #define fc_SHIFT				1
3272 #define fc_MASK					0x00000001
3273 #define fc_WORD					word3
3274 #define nic_SHIFT				2
3275 #define nic_MASK				0x00000001
3276 #define nic_WORD				word3
3277 #define iscsi_SHIFT				3
3278 #define iscsi_MASK				0x00000001
3279 #define iscsi_WORD				word3
3280 #define rdma_SHIFT				4
3281 #define rdma_MASK				0x00000001
3282 #define rdma_WORD				word3
3283 	uint32_t sge_supp_len;
3284 #define SLI4_PAGE_SIZE 4096
3285 	uint32_t word5;
3286 #define if_page_sz_SHIFT			0
3287 #define if_page_sz_MASK				0x0000ffff
3288 #define if_page_sz_WORD				word5
3289 #define loopbk_scope_SHIFT			24
3290 #define loopbk_scope_MASK			0x0000000f
3291 #define loopbk_scope_WORD			word5
3292 #define rq_db_window_SHIFT			28
3293 #define rq_db_window_MASK			0x0000000f
3294 #define rq_db_window_WORD			word5
3295 	uint32_t word6;
3296 #define eq_pages_SHIFT				0
3297 #define eq_pages_MASK				0x0000000f
3298 #define eq_pages_WORD				word6
3299 #define eqe_size_SHIFT				8
3300 #define eqe_size_MASK				0x000000ff
3301 #define eqe_size_WORD				word6
3302 	uint32_t word7;
3303 #define cq_pages_SHIFT				0
3304 #define cq_pages_MASK				0x0000000f
3305 #define cq_pages_WORD				word7
3306 #define cqe_size_SHIFT				8
3307 #define cqe_size_MASK				0x000000ff
3308 #define cqe_size_WORD				word7
3309 	uint32_t word8;
3310 #define mq_pages_SHIFT				0
3311 #define mq_pages_MASK				0x0000000f
3312 #define mq_pages_WORD				word8
3313 #define mqe_size_SHIFT				8
3314 #define mqe_size_MASK				0x000000ff
3315 #define mqe_size_WORD				word8
3316 #define mq_elem_cnt_SHIFT			16
3317 #define mq_elem_cnt_MASK			0x000000ff
3318 #define mq_elem_cnt_WORD			word8
3319 	uint32_t word9;
3320 #define wq_pages_SHIFT				0
3321 #define wq_pages_MASK				0x0000ffff
3322 #define wq_pages_WORD				word9
3323 #define wqe_size_SHIFT				8
3324 #define wqe_size_MASK				0x000000ff
3325 #define wqe_size_WORD				word9
3326 	uint32_t word10;
3327 #define rq_pages_SHIFT				0
3328 #define rq_pages_MASK				0x0000ffff
3329 #define rq_pages_WORD				word10
3330 #define rqe_size_SHIFT				8
3331 #define rqe_size_MASK				0x000000ff
3332 #define rqe_size_WORD				word10
3333 	uint32_t word11;
3334 #define hdr_pages_SHIFT				0
3335 #define hdr_pages_MASK				0x0000000f
3336 #define hdr_pages_WORD				word11
3337 #define hdr_size_SHIFT				8
3338 #define hdr_size_MASK				0x0000000f
3339 #define hdr_size_WORD				word11
3340 #define hdr_pp_align_SHIFT			16
3341 #define hdr_pp_align_MASK			0x0000ffff
3342 #define hdr_pp_align_WORD			word11
3343 	uint32_t word12;
3344 #define sgl_pages_SHIFT				0
3345 #define sgl_pages_MASK				0x0000000f
3346 #define sgl_pages_WORD				word12
3347 #define sgl_pp_align_SHIFT			16
3348 #define sgl_pp_align_MASK			0x0000ffff
3349 #define sgl_pp_align_WORD			word12
3350 	uint32_t rsvd_13_63[51];
3351 };
3352 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3353 			       &(~((SLI4_PAGE_SIZE)-1)))
3354 
3355 struct lpfc_sli4_parameters {
3356 	uint32_t word0;
3357 #define cfg_prot_type_SHIFT			0
3358 #define cfg_prot_type_MASK			0x000000FF
3359 #define cfg_prot_type_WORD			word0
3360 	uint32_t word1;
3361 #define cfg_ft_SHIFT				0
3362 #define cfg_ft_MASK				0x00000001
3363 #define cfg_ft_WORD				word1
3364 #define cfg_sli_rev_SHIFT			4
3365 #define cfg_sli_rev_MASK			0x0000000f
3366 #define cfg_sli_rev_WORD			word1
3367 #define cfg_sli_family_SHIFT			8
3368 #define cfg_sli_family_MASK			0x0000000f
3369 #define cfg_sli_family_WORD			word1
3370 #define cfg_if_type_SHIFT			12
3371 #define cfg_if_type_MASK			0x0000000f
3372 #define cfg_if_type_WORD			word1
3373 #define cfg_sli_hint_1_SHIFT			16
3374 #define cfg_sli_hint_1_MASK			0x000000ff
3375 #define cfg_sli_hint_1_WORD			word1
3376 #define cfg_sli_hint_2_SHIFT			24
3377 #define cfg_sli_hint_2_MASK			0x0000001f
3378 #define cfg_sli_hint_2_WORD			word1
3379 	uint32_t word2;
3380 #define cfg_eqav_SHIFT				31
3381 #define cfg_eqav_MASK				0x00000001
3382 #define cfg_eqav_WORD				word2
3383 	uint32_t word3;
3384 	uint32_t word4;
3385 #define cfg_cqv_SHIFT				14
3386 #define cfg_cqv_MASK				0x00000003
3387 #define cfg_cqv_WORD				word4
3388 #define cfg_cqpsize_SHIFT			16
3389 #define cfg_cqpsize_MASK			0x000000ff
3390 #define cfg_cqpsize_WORD			word4
3391 #define cfg_cqav_SHIFT				31
3392 #define cfg_cqav_MASK				0x00000001
3393 #define cfg_cqav_WORD				word4
3394 	uint32_t word5;
3395 	uint32_t word6;
3396 #define cfg_mqv_SHIFT				14
3397 #define cfg_mqv_MASK				0x00000003
3398 #define cfg_mqv_WORD				word6
3399 	uint32_t word7;
3400 	uint32_t word8;
3401 #define cfg_wqpcnt_SHIFT			0
3402 #define cfg_wqpcnt_MASK				0x0000000f
3403 #define cfg_wqpcnt_WORD				word8
3404 #define cfg_wqsize_SHIFT			8
3405 #define cfg_wqsize_MASK				0x0000000f
3406 #define cfg_wqsize_WORD				word8
3407 #define cfg_wqv_SHIFT				14
3408 #define cfg_wqv_MASK				0x00000003
3409 #define cfg_wqv_WORD				word8
3410 #define cfg_wqpsize_SHIFT			16
3411 #define cfg_wqpsize_MASK			0x000000ff
3412 #define cfg_wqpsize_WORD			word8
3413 	uint32_t word9;
3414 	uint32_t word10;
3415 #define cfg_rqv_SHIFT				14
3416 #define cfg_rqv_MASK				0x00000003
3417 #define cfg_rqv_WORD				word10
3418 	uint32_t word11;
3419 #define cfg_rq_db_window_SHIFT			28
3420 #define cfg_rq_db_window_MASK			0x0000000f
3421 #define cfg_rq_db_window_WORD			word11
3422 	uint32_t word12;
3423 #define cfg_fcoe_SHIFT				0
3424 #define cfg_fcoe_MASK				0x00000001
3425 #define cfg_fcoe_WORD				word12
3426 #define cfg_ext_SHIFT				1
3427 #define cfg_ext_MASK				0x00000001
3428 #define cfg_ext_WORD				word12
3429 #define cfg_hdrr_SHIFT				2
3430 #define cfg_hdrr_MASK				0x00000001
3431 #define cfg_hdrr_WORD				word12
3432 #define cfg_phwq_SHIFT				15
3433 #define cfg_phwq_MASK				0x00000001
3434 #define cfg_phwq_WORD				word12
3435 #define cfg_oas_SHIFT				25
3436 #define cfg_oas_MASK				0x00000001
3437 #define cfg_oas_WORD				word12
3438 #define cfg_loopbk_scope_SHIFT			28
3439 #define cfg_loopbk_scope_MASK			0x0000000f
3440 #define cfg_loopbk_scope_WORD			word12
3441 	uint32_t sge_supp_len;
3442 	uint32_t word14;
3443 #define cfg_sgl_page_cnt_SHIFT			0
3444 #define cfg_sgl_page_cnt_MASK			0x0000000f
3445 #define cfg_sgl_page_cnt_WORD			word14
3446 #define cfg_sgl_page_size_SHIFT			8
3447 #define cfg_sgl_page_size_MASK			0x000000ff
3448 #define cfg_sgl_page_size_WORD			word14
3449 #define cfg_sgl_pp_align_SHIFT			16
3450 #define cfg_sgl_pp_align_MASK			0x000000ff
3451 #define cfg_sgl_pp_align_WORD			word14
3452 	uint32_t word15;
3453 	uint32_t word16;
3454 	uint32_t word17;
3455 	uint32_t word18;
3456 	uint32_t word19;
3457 #define cfg_ext_embed_cb_SHIFT			0
3458 #define cfg_ext_embed_cb_MASK			0x00000001
3459 #define cfg_ext_embed_cb_WORD			word19
3460 #define cfg_mds_diags_SHIFT			1
3461 #define cfg_mds_diags_MASK			0x00000001
3462 #define cfg_mds_diags_WORD			word19
3463 #define cfg_nvme_SHIFT				3
3464 #define cfg_nvme_MASK				0x00000001
3465 #define cfg_nvme_WORD				word19
3466 #define cfg_xib_SHIFT				4
3467 #define cfg_xib_MASK				0x00000001
3468 #define cfg_xib_WORD				word19
3469 #define cfg_xpsgl_SHIFT				6
3470 #define cfg_xpsgl_MASK				0x00000001
3471 #define cfg_xpsgl_WORD				word19
3472 #define cfg_eqdr_SHIFT				8
3473 #define cfg_eqdr_MASK				0x00000001
3474 #define cfg_eqdr_WORD				word19
3475 #define cfg_nosr_SHIFT				9
3476 #define cfg_nosr_MASK				0x00000001
3477 #define cfg_nosr_WORD				word19
3478 
3479 #define cfg_bv1s_SHIFT                          10
3480 #define cfg_bv1s_MASK                           0x00000001
3481 #define cfg_bv1s_WORD                           word19
3482 
3483 #define cfg_nsler_SHIFT                         12
3484 #define cfg_nsler_MASK                          0x00000001
3485 #define cfg_nsler_WORD                          word19
3486 
3487 	uint32_t word20;
3488 #define cfg_max_tow_xri_SHIFT			0
3489 #define cfg_max_tow_xri_MASK			0x0000ffff
3490 #define cfg_max_tow_xri_WORD			word20
3491 
3492 	uint32_t word21;                        /* RESERVED */
3493 	uint32_t word22;                        /* RESERVED */
3494 	uint32_t word23;                        /* RESERVED */
3495 
3496 	uint32_t word24;
3497 #define cfg_frag_field_offset_SHIFT		0
3498 #define cfg_frag_field_offset_MASK		0x0000ffff
3499 #define cfg_frag_field_offset_WORD		word24
3500 
3501 #define cfg_frag_field_size_SHIFT		16
3502 #define cfg_frag_field_size_MASK		0x0000ffff
3503 #define cfg_frag_field_size_WORD		word24
3504 
3505 	uint32_t word25;
3506 #define cfg_sgl_field_offset_SHIFT		0
3507 #define cfg_sgl_field_offset_MASK		0x0000ffff
3508 #define cfg_sgl_field_offset_WORD		word25
3509 
3510 #define cfg_sgl_field_size_SHIFT		16
3511 #define cfg_sgl_field_size_MASK			0x0000ffff
3512 #define cfg_sgl_field_size_WORD			word25
3513 
3514 	uint32_t word26;	/* Chain SGE initial value LOW  */
3515 	uint32_t word27;	/* Chain SGE initial value HIGH */
3516 #define LPFC_NODELAY_MAX_IO			32
3517 };
3518 
3519 #define LPFC_SET_UE_RECOVERY		0x10
3520 #define LPFC_SET_MDS_DIAGS		0x11
3521 struct lpfc_mbx_set_feature {
3522 	struct mbox_header header;
3523 	uint32_t feature;
3524 	uint32_t param_len;
3525 	uint32_t word6;
3526 #define lpfc_mbx_set_feature_UER_SHIFT  0
3527 #define lpfc_mbx_set_feature_UER_MASK   0x00000001
3528 #define lpfc_mbx_set_feature_UER_WORD   word6
3529 #define lpfc_mbx_set_feature_mds_SHIFT  0
3530 #define lpfc_mbx_set_feature_mds_MASK   0x00000001
3531 #define lpfc_mbx_set_feature_mds_WORD   word6
3532 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT  1
3533 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK   0x00000001
3534 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD   word6
3535 	uint32_t word7;
3536 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3537 #define lpfc_mbx_set_feature_UERP_MASK  0x0000ffff
3538 #define lpfc_mbx_set_feature_UERP_WORD  word7
3539 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3540 #define lpfc_mbx_set_feature_UESR_MASK  0x0000ffff
3541 #define lpfc_mbx_set_feature_UESR_WORD  word7
3542 };
3543 
3544 
3545 #define LPFC_SET_HOST_OS_DRIVER_VERSION    0x2
3546 struct lpfc_mbx_set_host_data {
3547 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE   48
3548 	struct mbox_header header;
3549 	uint32_t param_id;
3550 	uint32_t param_len;
3551 	uint8_t  data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3552 };
3553 
3554 struct lpfc_mbx_set_trunk_mode {
3555 	struct mbox_header header;
3556 	uint32_t word0;
3557 #define lpfc_mbx_set_trunk_mode_WORD      word0
3558 #define lpfc_mbx_set_trunk_mode_SHIFT     0
3559 #define lpfc_mbx_set_trunk_mode_MASK      0xFF
3560 	uint32_t word1;
3561 	uint32_t word2;
3562 };
3563 
3564 struct lpfc_mbx_get_sli4_parameters {
3565 	struct mbox_header header;
3566 	struct lpfc_sli4_parameters sli4_parameters;
3567 };
3568 
3569 struct lpfc_rscr_desc_generic {
3570 #define LPFC_RSRC_DESC_WSIZE			22
3571 	uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3572 };
3573 
3574 struct lpfc_rsrc_desc_pcie {
3575 	uint32_t word0;
3576 #define lpfc_rsrc_desc_pcie_type_SHIFT		0
3577 #define lpfc_rsrc_desc_pcie_type_MASK		0x000000ff
3578 #define lpfc_rsrc_desc_pcie_type_WORD		word0
3579 #define LPFC_RSRC_DESC_TYPE_PCIE		0x40
3580 #define lpfc_rsrc_desc_pcie_length_SHIFT	8
3581 #define lpfc_rsrc_desc_pcie_length_MASK		0x000000ff
3582 #define lpfc_rsrc_desc_pcie_length_WORD		word0
3583 	uint32_t word1;
3584 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT		0
3585 #define lpfc_rsrc_desc_pcie_pfnum_MASK		0x000000ff
3586 #define lpfc_rsrc_desc_pcie_pfnum_WORD		word1
3587 	uint32_t reserved;
3588 	uint32_t word3;
3589 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT	0
3590 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK	0x000000ff
3591 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD	word3
3592 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT	8
3593 #define lpfc_rsrc_desc_pcie_pf_sta_MASK		0x000000ff
3594 #define lpfc_rsrc_desc_pcie_pf_sta_WORD		word3
3595 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT	16
3596 #define lpfc_rsrc_desc_pcie_pf_type_MASK	0x000000ff
3597 #define lpfc_rsrc_desc_pcie_pf_type_WORD	word3
3598 	uint32_t word4;
3599 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT	0
3600 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK	0x0000ffff
3601 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD	word4
3602 };
3603 
3604 struct lpfc_rsrc_desc_fcfcoe {
3605 	uint32_t word0;
3606 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT	0
3607 #define lpfc_rsrc_desc_fcfcoe_type_MASK		0x000000ff
3608 #define lpfc_rsrc_desc_fcfcoe_type_WORD		word0
3609 #define LPFC_RSRC_DESC_TYPE_FCFCOE		0x43
3610 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT	8
3611 #define lpfc_rsrc_desc_fcfcoe_length_MASK	0x000000ff
3612 #define lpfc_rsrc_desc_fcfcoe_length_WORD	word0
3613 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD	0
3614 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH	72
3615 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH	88
3616 	uint32_t word1;
3617 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT	0
3618 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK	0x000000ff
3619 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD	word1
3620 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT	16
3621 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK        0x000007ff
3622 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD        word1
3623 	uint32_t word2;
3624 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT	0
3625 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK	0x0000ffff
3626 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD	word2
3627 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT	16
3628 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK	0x0000ffff
3629 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD	word2
3630 	uint32_t word3;
3631 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT	0
3632 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK	0x0000ffff
3633 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD	word3
3634 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT	16
3635 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK	0x0000ffff
3636 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD	word3
3637 	uint32_t word4;
3638 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT	0
3639 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK	0x0000ffff
3640 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD	word4
3641 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT	16
3642 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK	0x0000ffff
3643 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD	word4
3644 	uint32_t word5;
3645 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT	0
3646 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK	0x0000ffff
3647 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD	word5
3648 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT	16
3649 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK	0x0000ffff
3650 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD	word5
3651 	uint32_t word6;
3652 	uint32_t word7;
3653 	uint32_t word8;
3654 	uint32_t word9;
3655 	uint32_t word10;
3656 	uint32_t word11;
3657 	uint32_t word12;
3658 	uint32_t word13;
3659 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT	0
3660 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK	0x0000003f
3661 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD	word13
3662 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT      6
3663 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK	0x00000003
3664 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD	word13
3665 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT		8
3666 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK		0x00000001
3667 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD		word13
3668 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT		9
3669 #define lpfc_rsrc_desc_fcfcoe_lld_MASK		0x00000001
3670 #define lpfc_rsrc_desc_fcfcoe_lld_WORD		word13
3671 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT	16
3672 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK	0x0000ffff
3673 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD	word13
3674 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3675 	uint32_t bw_min;
3676 	uint32_t bw_max;
3677 	uint32_t iops_min;
3678 	uint32_t iops_max;
3679 	uint32_t reserved[4];
3680 };
3681 
3682 struct lpfc_func_cfg {
3683 #define LPFC_RSRC_DESC_MAX_NUM			2
3684 	uint32_t rsrc_desc_count;
3685 	struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3686 };
3687 
3688 struct lpfc_mbx_get_func_cfg {
3689 	struct mbox_header header;
3690 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE	0x0
3691 #define LPFC_CFG_TYPE_FACTURY_DEFAULT		0x1
3692 #define LPFC_CFG_TYPE_CURRENT_ACTIVE		0x2
3693 	struct lpfc_func_cfg func_cfg;
3694 };
3695 
3696 struct lpfc_prof_cfg {
3697 #define LPFC_RSRC_DESC_MAX_NUM			2
3698 	uint32_t rsrc_desc_count;
3699 	struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3700 };
3701 
3702 struct lpfc_mbx_get_prof_cfg {
3703 	struct mbox_header header;
3704 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE	0x0
3705 #define LPFC_CFG_TYPE_FACTURY_DEFAULT		0x1
3706 #define LPFC_CFG_TYPE_CURRENT_ACTIVE		0x2
3707 	union {
3708 		struct {
3709 			uint32_t word10;
3710 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT	0
3711 #define lpfc_mbx_get_prof_cfg_prof_id_MASK	0x000000ff
3712 #define lpfc_mbx_get_prof_cfg_prof_id_WORD	word10
3713 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT	8
3714 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK	0x00000003
3715 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD	word10
3716 		} request;
3717 		struct {
3718 			struct lpfc_prof_cfg prof_cfg;
3719 		} response;
3720 	} u;
3721 };
3722 
3723 struct lpfc_controller_attribute {
3724 	uint32_t version_string[8];
3725 	uint32_t manufacturer_name[8];
3726 	uint32_t supported_modes;
3727 	uint32_t word17;
3728 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT	0
3729 #define lpfc_cntl_attr_eprom_ver_lo_MASK	0x000000ff
3730 #define lpfc_cntl_attr_eprom_ver_lo_WORD	word17
3731 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT	8
3732 #define lpfc_cntl_attr_eprom_ver_hi_MASK	0x000000ff
3733 #define lpfc_cntl_attr_eprom_ver_hi_WORD	word17
3734 	uint32_t mbx_da_struct_ver;
3735 	uint32_t ep_fw_da_struct_ver;
3736 	uint32_t ncsi_ver_str[3];
3737 	uint32_t dflt_ext_timeout;
3738 	uint32_t model_number[8];
3739 	uint32_t description[16];
3740 	uint32_t serial_number[8];
3741 	uint32_t ip_ver_str[8];
3742 	uint32_t fw_ver_str[8];
3743 	uint32_t bios_ver_str[8];
3744 	uint32_t redboot_ver_str[8];
3745 	uint32_t driver_ver_str[8];
3746 	uint32_t flash_fw_ver_str[8];
3747 	uint32_t functionality;
3748 	uint32_t word105;
3749 #define lpfc_cntl_attr_max_cbd_len_SHIFT	0
3750 #define lpfc_cntl_attr_max_cbd_len_MASK		0x0000ffff
3751 #define lpfc_cntl_attr_max_cbd_len_WORD		word105
3752 #define lpfc_cntl_attr_asic_rev_SHIFT		16
3753 #define lpfc_cntl_attr_asic_rev_MASK		0x000000ff
3754 #define lpfc_cntl_attr_asic_rev_WORD		word105
3755 #define lpfc_cntl_attr_gen_guid0_SHIFT		24
3756 #define lpfc_cntl_attr_gen_guid0_MASK		0x000000ff
3757 #define lpfc_cntl_attr_gen_guid0_WORD		word105
3758 	uint32_t gen_guid1_12[3];
3759 	uint32_t word109;
3760 #define lpfc_cntl_attr_gen_guid13_14_SHIFT	0
3761 #define lpfc_cntl_attr_gen_guid13_14_MASK	0x0000ffff
3762 #define lpfc_cntl_attr_gen_guid13_14_WORD	word109
3763 #define lpfc_cntl_attr_gen_guid15_SHIFT		16
3764 #define lpfc_cntl_attr_gen_guid15_MASK		0x000000ff
3765 #define lpfc_cntl_attr_gen_guid15_WORD		word109
3766 #define lpfc_cntl_attr_hba_port_cnt_SHIFT	24
3767 #define lpfc_cntl_attr_hba_port_cnt_MASK	0x000000ff
3768 #define lpfc_cntl_attr_hba_port_cnt_WORD	word109
3769 	uint32_t word110;
3770 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT	0
3771 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK	0x0000ffff
3772 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD	word110
3773 #define lpfc_cntl_attr_multi_func_dev_SHIFT	24
3774 #define lpfc_cntl_attr_multi_func_dev_MASK	0x000000ff
3775 #define lpfc_cntl_attr_multi_func_dev_WORD	word110
3776 	uint32_t word111;
3777 #define lpfc_cntl_attr_cache_valid_SHIFT	0
3778 #define lpfc_cntl_attr_cache_valid_MASK		0x000000ff
3779 #define lpfc_cntl_attr_cache_valid_WORD		word111
3780 #define lpfc_cntl_attr_hba_status_SHIFT		8
3781 #define lpfc_cntl_attr_hba_status_MASK		0x000000ff
3782 #define lpfc_cntl_attr_hba_status_WORD		word111
3783 #define lpfc_cntl_attr_max_domain_SHIFT		16
3784 #define lpfc_cntl_attr_max_domain_MASK		0x000000ff
3785 #define lpfc_cntl_attr_max_domain_WORD		word111
3786 #define lpfc_cntl_attr_lnk_numb_SHIFT		24
3787 #define lpfc_cntl_attr_lnk_numb_MASK		0x0000003f
3788 #define lpfc_cntl_attr_lnk_numb_WORD		word111
3789 #define lpfc_cntl_attr_lnk_type_SHIFT		30
3790 #define lpfc_cntl_attr_lnk_type_MASK		0x00000003
3791 #define lpfc_cntl_attr_lnk_type_WORD		word111
3792 	uint32_t fw_post_status;
3793 	uint32_t hba_mtu[8];
3794 	uint32_t word121;
3795 	uint32_t reserved1[3];
3796 	uint32_t word125;
3797 #define lpfc_cntl_attr_pci_vendor_id_SHIFT	0
3798 #define lpfc_cntl_attr_pci_vendor_id_MASK	0x0000ffff
3799 #define lpfc_cntl_attr_pci_vendor_id_WORD	word125
3800 #define lpfc_cntl_attr_pci_device_id_SHIFT	16
3801 #define lpfc_cntl_attr_pci_device_id_MASK	0x0000ffff
3802 #define lpfc_cntl_attr_pci_device_id_WORD	word125
3803 	uint32_t word126;
3804 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT	0
3805 #define lpfc_cntl_attr_pci_subvdr_id_MASK	0x0000ffff
3806 #define lpfc_cntl_attr_pci_subvdr_id_WORD	word126
3807 #define lpfc_cntl_attr_pci_subsys_id_SHIFT	16
3808 #define lpfc_cntl_attr_pci_subsys_id_MASK	0x0000ffff
3809 #define lpfc_cntl_attr_pci_subsys_id_WORD	word126
3810 	uint32_t word127;
3811 #define lpfc_cntl_attr_pci_bus_num_SHIFT	0
3812 #define lpfc_cntl_attr_pci_bus_num_MASK		0x000000ff
3813 #define lpfc_cntl_attr_pci_bus_num_WORD		word127
3814 #define lpfc_cntl_attr_pci_dev_num_SHIFT	8
3815 #define lpfc_cntl_attr_pci_dev_num_MASK		0x000000ff
3816 #define lpfc_cntl_attr_pci_dev_num_WORD		word127
3817 #define lpfc_cntl_attr_pci_fnc_num_SHIFT	16
3818 #define lpfc_cntl_attr_pci_fnc_num_MASK		0x000000ff
3819 #define lpfc_cntl_attr_pci_fnc_num_WORD		word127
3820 #define lpfc_cntl_attr_inf_type_SHIFT		24
3821 #define lpfc_cntl_attr_inf_type_MASK		0x000000ff
3822 #define lpfc_cntl_attr_inf_type_WORD		word127
3823 	uint32_t unique_id[2];
3824 	uint32_t word130;
3825 #define lpfc_cntl_attr_num_netfil_SHIFT		0
3826 #define lpfc_cntl_attr_num_netfil_MASK		0x000000ff
3827 #define lpfc_cntl_attr_num_netfil_WORD		word130
3828 	uint32_t reserved2[4];
3829 };
3830 
3831 struct lpfc_mbx_get_cntl_attributes {
3832 	union  lpfc_sli4_cfg_shdr cfg_shdr;
3833 	struct lpfc_controller_attribute cntl_attr;
3834 };
3835 
3836 struct lpfc_mbx_get_port_name {
3837 	struct mbox_header header;
3838 	union {
3839 		struct {
3840 			uint32_t word4;
3841 #define lpfc_mbx_get_port_name_lnk_type_SHIFT	0
3842 #define lpfc_mbx_get_port_name_lnk_type_MASK	0x00000003
3843 #define lpfc_mbx_get_port_name_lnk_type_WORD	word4
3844 		} request;
3845 		struct {
3846 			uint32_t word4;
3847 #define lpfc_mbx_get_port_name_name0_SHIFT	0
3848 #define lpfc_mbx_get_port_name_name0_MASK	0x000000FF
3849 #define lpfc_mbx_get_port_name_name0_WORD	word4
3850 #define lpfc_mbx_get_port_name_name1_SHIFT	8
3851 #define lpfc_mbx_get_port_name_name1_MASK	0x000000FF
3852 #define lpfc_mbx_get_port_name_name1_WORD	word4
3853 #define lpfc_mbx_get_port_name_name2_SHIFT	16
3854 #define lpfc_mbx_get_port_name_name2_MASK	0x000000FF
3855 #define lpfc_mbx_get_port_name_name2_WORD	word4
3856 #define lpfc_mbx_get_port_name_name3_SHIFT	24
3857 #define lpfc_mbx_get_port_name_name3_MASK	0x000000FF
3858 #define lpfc_mbx_get_port_name_name3_WORD	word4
3859 #define LPFC_LINK_NUMBER_0			0
3860 #define LPFC_LINK_NUMBER_1			1
3861 #define LPFC_LINK_NUMBER_2			2
3862 #define LPFC_LINK_NUMBER_3			3
3863 		} response;
3864 	} u;
3865 };
3866 
3867 /* Mailbox Completion Queue Error Messages */
3868 #define MB_CQE_STATUS_SUCCESS			0x0
3869 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES	0x1
3870 #define MB_CQE_STATUS_INVALID_PARAMETER		0x2
3871 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES	0x3
3872 #define MB_CEQ_STATUS_QUEUE_FLUSHING		0x4
3873 #define MB_CQE_STATUS_DMA_FAILED		0x5
3874 
3875 #define LPFC_MBX_WR_CONFIG_MAX_BDE		1
3876 struct lpfc_mbx_wr_object {
3877 	struct mbox_header header;
3878 	union {
3879 		struct {
3880 			uint32_t word4;
3881 #define lpfc_wr_object_eof_SHIFT		31
3882 #define lpfc_wr_object_eof_MASK			0x00000001
3883 #define lpfc_wr_object_eof_WORD			word4
3884 #define lpfc_wr_object_eas_SHIFT		29
3885 #define lpfc_wr_object_eas_MASK			0x00000001
3886 #define lpfc_wr_object_eas_WORD			word4
3887 #define lpfc_wr_object_write_length_SHIFT	0
3888 #define lpfc_wr_object_write_length_MASK	0x00FFFFFF
3889 #define lpfc_wr_object_write_length_WORD	word4
3890 			uint32_t write_offset;
3891 			uint32_t object_name[26];
3892 			uint32_t bde_count;
3893 			struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3894 		} request;
3895 		struct {
3896 			uint32_t actual_write_length;
3897 			uint32_t word5;
3898 #define lpfc_wr_object_change_status_SHIFT	0
3899 #define lpfc_wr_object_change_status_MASK	0x000000FF
3900 #define lpfc_wr_object_change_status_WORD	word5
3901 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED	0x00
3902 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET	0x01
3903 #define LPFC_CHANGE_STATUS_FW_RESET		0x02
3904 #define LPFC_CHANGE_STATUS_PORT_MIGRATION	0x04
3905 #define LPFC_CHANGE_STATUS_PCI_RESET		0x05
3906 		} response;
3907 	} u;
3908 };
3909 
3910 /* mailbox queue entry structure */
3911 struct lpfc_mqe {
3912 	uint32_t word0;
3913 #define lpfc_mqe_status_SHIFT		16
3914 #define lpfc_mqe_status_MASK		0x0000FFFF
3915 #define lpfc_mqe_status_WORD		word0
3916 #define lpfc_mqe_command_SHIFT		8
3917 #define lpfc_mqe_command_MASK		0x000000FF
3918 #define lpfc_mqe_command_WORD		word0
3919 	union {
3920 		uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3921 		/* sli4 mailbox commands */
3922 		struct lpfc_mbx_sli4_config sli4_config;
3923 		struct lpfc_mbx_init_vfi init_vfi;
3924 		struct lpfc_mbx_reg_vfi reg_vfi;
3925 		struct lpfc_mbx_reg_vfi unreg_vfi;
3926 		struct lpfc_mbx_init_vpi init_vpi;
3927 		struct lpfc_mbx_resume_rpi resume_rpi;
3928 		struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3929 		struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3930 		struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3931 		struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3932 		struct lpfc_mbx_reg_fcfi reg_fcfi;
3933 		struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3934 		struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3935 		struct lpfc_mbx_mq_create mq_create;
3936 		struct lpfc_mbx_mq_create_ext mq_create_ext;
3937 		struct lpfc_mbx_eq_create eq_create;
3938 		struct lpfc_mbx_modify_eq_delay eq_delay;
3939 		struct lpfc_mbx_cq_create cq_create;
3940 		struct lpfc_mbx_cq_create_set cq_create_set;
3941 		struct lpfc_mbx_wq_create wq_create;
3942 		struct lpfc_mbx_rq_create rq_create;
3943 		struct lpfc_mbx_rq_create_v2 rq_create_v2;
3944 		struct lpfc_mbx_mq_destroy mq_destroy;
3945 		struct lpfc_mbx_eq_destroy eq_destroy;
3946 		struct lpfc_mbx_cq_destroy cq_destroy;
3947 		struct lpfc_mbx_wq_destroy wq_destroy;
3948 		struct lpfc_mbx_rq_destroy rq_destroy;
3949 		struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3950 		struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3951 		struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3952 		struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3953 		struct lpfc_mbx_nembed_cmd nembed_cmd;
3954 		struct lpfc_mbx_read_rev read_rev;
3955 		struct lpfc_mbx_read_vpi read_vpi;
3956 		struct lpfc_mbx_read_config rd_config;
3957 		struct lpfc_mbx_request_features req_ftrs;
3958 		struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3959 		struct lpfc_mbx_query_fw_config query_fw_cfg;
3960 		struct lpfc_mbx_set_beacon_config beacon_config;
3961 		struct lpfc_mbx_supp_pages supp_pages;
3962 		struct lpfc_mbx_pc_sli4_params sli4_params;
3963 		struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3964 		struct lpfc_mbx_set_link_diag_state link_diag_state;
3965 		struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3966 		struct lpfc_mbx_run_link_diag_test link_diag_test;
3967 		struct lpfc_mbx_get_func_cfg get_func_cfg;
3968 		struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3969 		struct lpfc_mbx_wr_object wr_object;
3970 		struct lpfc_mbx_get_port_name get_port_name;
3971 		struct lpfc_mbx_set_feature  set_feature;
3972 		struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3973 		struct lpfc_mbx_set_host_data set_host_data;
3974 		struct lpfc_mbx_set_trunk_mode set_trunk_mode;
3975 		struct lpfc_mbx_nop nop;
3976 		struct lpfc_mbx_set_ras_fwlog ras_fwlog;
3977 	} un;
3978 };
3979 
3980 struct lpfc_mcqe {
3981 	uint32_t word0;
3982 #define lpfc_mcqe_status_SHIFT		0
3983 #define lpfc_mcqe_status_MASK		0x0000FFFF
3984 #define lpfc_mcqe_status_WORD		word0
3985 #define lpfc_mcqe_ext_status_SHIFT	16
3986 #define lpfc_mcqe_ext_status_MASK	0x0000FFFF
3987 #define lpfc_mcqe_ext_status_WORD	word0
3988 	uint32_t mcqe_tag0;
3989 	uint32_t mcqe_tag1;
3990 	uint32_t trailer;
3991 #define lpfc_trailer_valid_SHIFT	31
3992 #define lpfc_trailer_valid_MASK		0x00000001
3993 #define lpfc_trailer_valid_WORD		trailer
3994 #define lpfc_trailer_async_SHIFT	30
3995 #define lpfc_trailer_async_MASK		0x00000001
3996 #define lpfc_trailer_async_WORD		trailer
3997 #define lpfc_trailer_hpi_SHIFT		29
3998 #define lpfc_trailer_hpi_MASK		0x00000001
3999 #define lpfc_trailer_hpi_WORD		trailer
4000 #define lpfc_trailer_completed_SHIFT	28
4001 #define lpfc_trailer_completed_MASK	0x00000001
4002 #define lpfc_trailer_completed_WORD	trailer
4003 #define lpfc_trailer_consumed_SHIFT	27
4004 #define lpfc_trailer_consumed_MASK	0x00000001
4005 #define lpfc_trailer_consumed_WORD	trailer
4006 #define lpfc_trailer_type_SHIFT		16
4007 #define lpfc_trailer_type_MASK		0x000000FF
4008 #define lpfc_trailer_type_WORD		trailer
4009 #define lpfc_trailer_code_SHIFT		8
4010 #define lpfc_trailer_code_MASK		0x000000FF
4011 #define lpfc_trailer_code_WORD		trailer
4012 #define LPFC_TRAILER_CODE_LINK	0x1
4013 #define LPFC_TRAILER_CODE_FCOE	0x2
4014 #define LPFC_TRAILER_CODE_DCBX	0x3
4015 #define LPFC_TRAILER_CODE_GRP5	0x5
4016 #define LPFC_TRAILER_CODE_FC	0x10
4017 #define LPFC_TRAILER_CODE_SLI	0x11
4018 };
4019 
4020 struct lpfc_acqe_link {
4021 	uint32_t word0;
4022 #define lpfc_acqe_link_speed_SHIFT		24
4023 #define lpfc_acqe_link_speed_MASK		0x000000FF
4024 #define lpfc_acqe_link_speed_WORD		word0
4025 #define LPFC_ASYNC_LINK_SPEED_ZERO		0x0
4026 #define LPFC_ASYNC_LINK_SPEED_10MBPS		0x1
4027 #define LPFC_ASYNC_LINK_SPEED_100MBPS		0x2
4028 #define LPFC_ASYNC_LINK_SPEED_1GBPS		0x3
4029 #define LPFC_ASYNC_LINK_SPEED_10GBPS		0x4
4030 #define LPFC_ASYNC_LINK_SPEED_20GBPS		0x5
4031 #define LPFC_ASYNC_LINK_SPEED_25GBPS		0x6
4032 #define LPFC_ASYNC_LINK_SPEED_40GBPS		0x7
4033 #define LPFC_ASYNC_LINK_SPEED_100GBPS		0x8
4034 #define lpfc_acqe_link_duplex_SHIFT		16
4035 #define lpfc_acqe_link_duplex_MASK		0x000000FF
4036 #define lpfc_acqe_link_duplex_WORD		word0
4037 #define LPFC_ASYNC_LINK_DUPLEX_NONE		0x0
4038 #define LPFC_ASYNC_LINK_DUPLEX_HALF		0x1
4039 #define LPFC_ASYNC_LINK_DUPLEX_FULL		0x2
4040 #define lpfc_acqe_link_status_SHIFT		8
4041 #define lpfc_acqe_link_status_MASK		0x000000FF
4042 #define lpfc_acqe_link_status_WORD		word0
4043 #define LPFC_ASYNC_LINK_STATUS_DOWN		0x0
4044 #define LPFC_ASYNC_LINK_STATUS_UP		0x1
4045 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN	0x2
4046 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP	0x3
4047 #define lpfc_acqe_link_type_SHIFT		6
4048 #define lpfc_acqe_link_type_MASK		0x00000003
4049 #define lpfc_acqe_link_type_WORD		word0
4050 #define lpfc_acqe_link_number_SHIFT		0
4051 #define lpfc_acqe_link_number_MASK		0x0000003F
4052 #define lpfc_acqe_link_number_WORD		word0
4053 	uint32_t word1;
4054 #define lpfc_acqe_link_fault_SHIFT	0
4055 #define lpfc_acqe_link_fault_MASK	0x000000FF
4056 #define lpfc_acqe_link_fault_WORD	word1
4057 #define LPFC_ASYNC_LINK_FAULT_NONE	0x0
4058 #define LPFC_ASYNC_LINK_FAULT_LOCAL	0x1
4059 #define LPFC_ASYNC_LINK_FAULT_REMOTE	0x2
4060 #define LPFC_ASYNC_LINK_FAULT_LR_LRR	0x3
4061 #define lpfc_acqe_logical_link_speed_SHIFT	16
4062 #define lpfc_acqe_logical_link_speed_MASK	0x0000FFFF
4063 #define lpfc_acqe_logical_link_speed_WORD	word1
4064 	uint32_t event_tag;
4065 	uint32_t trailer;
4066 #define LPFC_LINK_EVENT_TYPE_PHYSICAL	0x0
4067 #define LPFC_LINK_EVENT_TYPE_VIRTUAL	0x1
4068 };
4069 
4070 struct lpfc_acqe_fip {
4071 	uint32_t index;
4072 	uint32_t word1;
4073 #define lpfc_acqe_fip_fcf_count_SHIFT		0
4074 #define lpfc_acqe_fip_fcf_count_MASK		0x0000FFFF
4075 #define lpfc_acqe_fip_fcf_count_WORD		word1
4076 #define lpfc_acqe_fip_event_type_SHIFT		16
4077 #define lpfc_acqe_fip_event_type_MASK		0x0000FFFF
4078 #define lpfc_acqe_fip_event_type_WORD		word1
4079 	uint32_t event_tag;
4080 	uint32_t trailer;
4081 #define LPFC_FIP_EVENT_TYPE_NEW_FCF		0x1
4082 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL	0x2
4083 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD		0x3
4084 #define LPFC_FIP_EVENT_TYPE_CVL			0x4
4085 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD	0x5
4086 };
4087 
4088 struct lpfc_acqe_dcbx {
4089 	uint32_t tlv_ttl;
4090 	uint32_t reserved;
4091 	uint32_t event_tag;
4092 	uint32_t trailer;
4093 };
4094 
4095 struct lpfc_acqe_grp5 {
4096 	uint32_t word0;
4097 #define lpfc_acqe_grp5_type_SHIFT		6
4098 #define lpfc_acqe_grp5_type_MASK		0x00000003
4099 #define lpfc_acqe_grp5_type_WORD		word0
4100 #define lpfc_acqe_grp5_number_SHIFT		0
4101 #define lpfc_acqe_grp5_number_MASK		0x0000003F
4102 #define lpfc_acqe_grp5_number_WORD		word0
4103 	uint32_t word1;
4104 #define lpfc_acqe_grp5_llink_spd_SHIFT	16
4105 #define lpfc_acqe_grp5_llink_spd_MASK	0x0000FFFF
4106 #define lpfc_acqe_grp5_llink_spd_WORD	word1
4107 	uint32_t event_tag;
4108 	uint32_t trailer;
4109 };
4110 
4111 extern const char *const trunk_errmsg[];
4112 
4113 struct lpfc_acqe_fc_la {
4114 	uint32_t word0;
4115 #define lpfc_acqe_fc_la_speed_SHIFT		24
4116 #define lpfc_acqe_fc_la_speed_MASK		0x000000FF
4117 #define lpfc_acqe_fc_la_speed_WORD		word0
4118 #define LPFC_FC_LA_SPEED_UNKNOWN		0x0
4119 #define LPFC_FC_LA_SPEED_1G		0x1
4120 #define LPFC_FC_LA_SPEED_2G		0x2
4121 #define LPFC_FC_LA_SPEED_4G		0x4
4122 #define LPFC_FC_LA_SPEED_8G		0x8
4123 #define LPFC_FC_LA_SPEED_10G		0xA
4124 #define LPFC_FC_LA_SPEED_16G		0x10
4125 #define LPFC_FC_LA_SPEED_32G            0x20
4126 #define LPFC_FC_LA_SPEED_64G            0x21
4127 #define LPFC_FC_LA_SPEED_128G           0x22
4128 #define LPFC_FC_LA_SPEED_256G           0x23
4129 #define lpfc_acqe_fc_la_topology_SHIFT		16
4130 #define lpfc_acqe_fc_la_topology_MASK		0x000000FF
4131 #define lpfc_acqe_fc_la_topology_WORD		word0
4132 #define LPFC_FC_LA_TOP_UNKOWN		0x0
4133 #define LPFC_FC_LA_TOP_P2P		0x1
4134 #define LPFC_FC_LA_TOP_FCAL		0x2
4135 #define LPFC_FC_LA_TOP_INTERNAL_LOOP	0x3
4136 #define LPFC_FC_LA_TOP_SERDES_LOOP	0x4
4137 #define lpfc_acqe_fc_la_att_type_SHIFT		8
4138 #define lpfc_acqe_fc_la_att_type_MASK		0x000000FF
4139 #define lpfc_acqe_fc_la_att_type_WORD		word0
4140 #define LPFC_FC_LA_TYPE_LINK_UP		0x1
4141 #define LPFC_FC_LA_TYPE_LINK_DOWN	0x2
4142 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA	0x3
4143 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN	0x4
4144 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK	0x5
4145 #define LPFC_FC_LA_TYPE_UNEXP_WWPN	0x6
4146 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT  0x7
4147 #define lpfc_acqe_fc_la_port_type_SHIFT		6
4148 #define lpfc_acqe_fc_la_port_type_MASK		0x00000003
4149 #define lpfc_acqe_fc_la_port_type_WORD		word0
4150 #define LPFC_LINK_TYPE_ETHERNET		0x0
4151 #define LPFC_LINK_TYPE_FC		0x1
4152 #define lpfc_acqe_fc_la_port_number_SHIFT	0
4153 #define lpfc_acqe_fc_la_port_number_MASK	0x0000003F
4154 #define lpfc_acqe_fc_la_port_number_WORD	word0
4155 
4156 /* Attention Type is 0x07 (Trunking Event) word0 */
4157 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT	16
4158 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK	0x0000001
4159 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD	word0
4160 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT	17
4161 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK	0x0000001
4162 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD	word0
4163 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT	18
4164 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK	0x0000001
4165 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD	word0
4166 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT	19
4167 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK	0x0000001
4168 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD	word0
4169 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT	20
4170 #define lpfc_acqe_fc_la_trunk_config_port0_MASK		0x0000001
4171 #define lpfc_acqe_fc_la_trunk_config_port0_WORD		word0
4172 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT	21
4173 #define lpfc_acqe_fc_la_trunk_config_port1_MASK		0x0000001
4174 #define lpfc_acqe_fc_la_trunk_config_port1_WORD		word0
4175 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT	22
4176 #define lpfc_acqe_fc_la_trunk_config_port2_MASK		0x0000001
4177 #define lpfc_acqe_fc_la_trunk_config_port2_WORD		word0
4178 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT	23
4179 #define lpfc_acqe_fc_la_trunk_config_port3_MASK		0x0000001
4180 #define lpfc_acqe_fc_la_trunk_config_port3_WORD		word0
4181 	uint32_t word1;
4182 #define lpfc_acqe_fc_la_llink_spd_SHIFT		16
4183 #define lpfc_acqe_fc_la_llink_spd_MASK		0x0000FFFF
4184 #define lpfc_acqe_fc_la_llink_spd_WORD		word1
4185 #define lpfc_acqe_fc_la_fault_SHIFT		0
4186 #define lpfc_acqe_fc_la_fault_MASK		0x000000FF
4187 #define lpfc_acqe_fc_la_fault_WORD		word1
4188 #define lpfc_acqe_fc_la_trunk_fault_SHIFT		0
4189 #define lpfc_acqe_fc_la_trunk_fault_MASK		0x0000000F
4190 #define lpfc_acqe_fc_la_trunk_fault_WORD		word1
4191 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT		4
4192 #define lpfc_acqe_fc_la_trunk_linkmask_MASK		0x000000F
4193 #define lpfc_acqe_fc_la_trunk_linkmask_WORD		word1
4194 #define LPFC_FC_LA_FAULT_NONE		0x0
4195 #define LPFC_FC_LA_FAULT_LOCAL		0x1
4196 #define LPFC_FC_LA_FAULT_REMOTE		0x2
4197 	uint32_t event_tag;
4198 	uint32_t trailer;
4199 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK		0x1
4200 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK	0x2
4201 };
4202 
4203 struct lpfc_acqe_misconfigured_event {
4204 	struct {
4205 	uint32_t word0;
4206 #define lpfc_sli_misconfigured_port0_state_SHIFT	0
4207 #define lpfc_sli_misconfigured_port0_state_MASK		0x000000FF
4208 #define lpfc_sli_misconfigured_port0_state_WORD		word0
4209 #define lpfc_sli_misconfigured_port1_state_SHIFT	8
4210 #define lpfc_sli_misconfigured_port1_state_MASK		0x000000FF
4211 #define lpfc_sli_misconfigured_port1_state_WORD		word0
4212 #define lpfc_sli_misconfigured_port2_state_SHIFT	16
4213 #define lpfc_sli_misconfigured_port2_state_MASK		0x000000FF
4214 #define lpfc_sli_misconfigured_port2_state_WORD		word0
4215 #define lpfc_sli_misconfigured_port3_state_SHIFT	24
4216 #define lpfc_sli_misconfigured_port3_state_MASK		0x000000FF
4217 #define lpfc_sli_misconfigured_port3_state_WORD		word0
4218 	uint32_t word1;
4219 #define lpfc_sli_misconfigured_port0_op_SHIFT		0
4220 #define lpfc_sli_misconfigured_port0_op_MASK		0x00000001
4221 #define lpfc_sli_misconfigured_port0_op_WORD		word1
4222 #define lpfc_sli_misconfigured_port0_severity_SHIFT	1
4223 #define lpfc_sli_misconfigured_port0_severity_MASK	0x00000003
4224 #define lpfc_sli_misconfigured_port0_severity_WORD	word1
4225 #define lpfc_sli_misconfigured_port1_op_SHIFT		8
4226 #define lpfc_sli_misconfigured_port1_op_MASK		0x00000001
4227 #define lpfc_sli_misconfigured_port1_op_WORD		word1
4228 #define lpfc_sli_misconfigured_port1_severity_SHIFT	9
4229 #define lpfc_sli_misconfigured_port1_severity_MASK	0x00000003
4230 #define lpfc_sli_misconfigured_port1_severity_WORD	word1
4231 #define lpfc_sli_misconfigured_port2_op_SHIFT		16
4232 #define lpfc_sli_misconfigured_port2_op_MASK		0x00000001
4233 #define lpfc_sli_misconfigured_port2_op_WORD		word1
4234 #define lpfc_sli_misconfigured_port2_severity_SHIFT	17
4235 #define lpfc_sli_misconfigured_port2_severity_MASK	0x00000003
4236 #define lpfc_sli_misconfigured_port2_severity_WORD	word1
4237 #define lpfc_sli_misconfigured_port3_op_SHIFT		24
4238 #define lpfc_sli_misconfigured_port3_op_MASK		0x00000001
4239 #define lpfc_sli_misconfigured_port3_op_WORD		word1
4240 #define lpfc_sli_misconfigured_port3_severity_SHIFT	25
4241 #define lpfc_sli_misconfigured_port3_severity_MASK	0x00000003
4242 #define lpfc_sli_misconfigured_port3_severity_WORD	word1
4243 	} theEvent;
4244 #define LPFC_SLI_EVENT_STATUS_VALID			0x00
4245 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT	0x01
4246 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE	0x02
4247 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED	0x03
4248 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED	0x04
4249 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED	0x05
4250 };
4251 
4252 struct lpfc_acqe_sli {
4253 	uint32_t event_data1;
4254 	uint32_t event_data2;
4255 	uint32_t reserved;
4256 	uint32_t trailer;
4257 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR		0x1
4258 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP		0x2
4259 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP		0x3
4260 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST		0x4
4261 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP		0x5
4262 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED	0x9
4263 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT	0xA
4264 };
4265 
4266 /*
4267  * Define the bootstrap mailbox (bmbx) region used to communicate
4268  * mailbox command between the host and port. The mailbox consists
4269  * of a payload area of 256 bytes and a completion queue of length
4270  * 16 bytes.
4271  */
4272 struct lpfc_bmbx_create {
4273 	struct lpfc_mqe mqe;
4274 	struct lpfc_mcqe mcqe;
4275 };
4276 
4277 #define SGL_ALIGN_SZ 64
4278 #define SGL_PAGE_SIZE 4096
4279 /* align SGL addr on a size boundary - adjust address up */
4280 #define NO_XRI  0xffff
4281 
4282 struct wqe_common {
4283 	uint32_t word6;
4284 #define wqe_xri_tag_SHIFT     0
4285 #define wqe_xri_tag_MASK      0x0000FFFF
4286 #define wqe_xri_tag_WORD      word6
4287 #define wqe_ctxt_tag_SHIFT    16
4288 #define wqe_ctxt_tag_MASK     0x0000FFFF
4289 #define wqe_ctxt_tag_WORD     word6
4290 	uint32_t word7;
4291 #define wqe_dif_SHIFT         0
4292 #define wqe_dif_MASK          0x00000003
4293 #define wqe_dif_WORD          word7
4294 #define LPFC_WQE_DIF_PASSTHRU	1
4295 #define LPFC_WQE_DIF_STRIP	2
4296 #define LPFC_WQE_DIF_INSERT	3
4297 #define wqe_ct_SHIFT          2
4298 #define wqe_ct_MASK           0x00000003
4299 #define wqe_ct_WORD           word7
4300 #define wqe_status_SHIFT      4
4301 #define wqe_status_MASK       0x0000000f
4302 #define wqe_status_WORD       word7
4303 #define wqe_cmnd_SHIFT        8
4304 #define wqe_cmnd_MASK         0x000000ff
4305 #define wqe_cmnd_WORD         word7
4306 #define wqe_class_SHIFT       16
4307 #define wqe_class_MASK        0x00000007
4308 #define wqe_class_WORD        word7
4309 #define wqe_ar_SHIFT          19
4310 #define wqe_ar_MASK           0x00000001
4311 #define wqe_ar_WORD           word7
4312 #define wqe_ag_SHIFT          wqe_ar_SHIFT
4313 #define wqe_ag_MASK           wqe_ar_MASK
4314 #define wqe_ag_WORD           wqe_ar_WORD
4315 #define wqe_pu_SHIFT          20
4316 #define wqe_pu_MASK           0x00000003
4317 #define wqe_pu_WORD           word7
4318 #define wqe_erp_SHIFT         22
4319 #define wqe_erp_MASK          0x00000001
4320 #define wqe_erp_WORD          word7
4321 #define wqe_conf_SHIFT        wqe_erp_SHIFT
4322 #define wqe_conf_MASK         wqe_erp_MASK
4323 #define wqe_conf_WORD         wqe_erp_WORD
4324 #define wqe_lnk_SHIFT         23
4325 #define wqe_lnk_MASK          0x00000001
4326 #define wqe_lnk_WORD          word7
4327 #define wqe_tmo_SHIFT         24
4328 #define wqe_tmo_MASK          0x000000ff
4329 #define wqe_tmo_WORD          word7
4330 	uint32_t abort_tag; /* word 8 in WQE */
4331 	uint32_t word9;
4332 #define wqe_reqtag_SHIFT      0
4333 #define wqe_reqtag_MASK       0x0000FFFF
4334 #define wqe_reqtag_WORD       word9
4335 #define wqe_temp_rpi_SHIFT    16
4336 #define wqe_temp_rpi_MASK     0x0000FFFF
4337 #define wqe_temp_rpi_WORD     word9
4338 #define wqe_rcvoxid_SHIFT     16
4339 #define wqe_rcvoxid_MASK      0x0000FFFF
4340 #define wqe_rcvoxid_WORD      word9
4341 #define wqe_sof_SHIFT         24
4342 #define wqe_sof_MASK          0x000000FF
4343 #define wqe_sof_WORD          word9
4344 #define wqe_eof_SHIFT         16
4345 #define wqe_eof_MASK          0x000000FF
4346 #define wqe_eof_WORD          word9
4347 	uint32_t word10;
4348 #define wqe_ebde_cnt_SHIFT    0
4349 #define wqe_ebde_cnt_MASK     0x0000000f
4350 #define wqe_ebde_cnt_WORD     word10
4351 #define wqe_nvme_SHIFT        4
4352 #define wqe_nvme_MASK         0x00000001
4353 #define wqe_nvme_WORD         word10
4354 #define wqe_oas_SHIFT         6
4355 #define wqe_oas_MASK          0x00000001
4356 #define wqe_oas_WORD          word10
4357 #define wqe_lenloc_SHIFT      7
4358 #define wqe_lenloc_MASK       0x00000003
4359 #define wqe_lenloc_WORD       word10
4360 #define LPFC_WQE_LENLOC_NONE		0
4361 #define LPFC_WQE_LENLOC_WORD3	1
4362 #define LPFC_WQE_LENLOC_WORD12	2
4363 #define LPFC_WQE_LENLOC_WORD4	3
4364 #define wqe_qosd_SHIFT        9
4365 #define wqe_qosd_MASK         0x00000001
4366 #define wqe_qosd_WORD         word10
4367 #define wqe_xbl_SHIFT         11
4368 #define wqe_xbl_MASK          0x00000001
4369 #define wqe_xbl_WORD          word10
4370 #define wqe_iod_SHIFT         13
4371 #define wqe_iod_MASK          0x00000001
4372 #define wqe_iod_WORD          word10
4373 #define LPFC_WQE_IOD_NONE	0
4374 #define LPFC_WQE_IOD_WRITE	0
4375 #define LPFC_WQE_IOD_READ	1
4376 #define wqe_dbde_SHIFT        14
4377 #define wqe_dbde_MASK         0x00000001
4378 #define wqe_dbde_WORD         word10
4379 #define wqe_wqes_SHIFT        15
4380 #define wqe_wqes_MASK         0x00000001
4381 #define wqe_wqes_WORD         word10
4382 /* Note that this field overlaps above fields */
4383 #define wqe_wqid_SHIFT        1
4384 #define wqe_wqid_MASK         0x00007fff
4385 #define wqe_wqid_WORD         word10
4386 #define wqe_pri_SHIFT         16
4387 #define wqe_pri_MASK          0x00000007
4388 #define wqe_pri_WORD          word10
4389 #define wqe_pv_SHIFT          19
4390 #define wqe_pv_MASK           0x00000001
4391 #define wqe_pv_WORD           word10
4392 #define wqe_xc_SHIFT          21
4393 #define wqe_xc_MASK           0x00000001
4394 #define wqe_xc_WORD           word10
4395 #define wqe_sr_SHIFT          22
4396 #define wqe_sr_MASK           0x00000001
4397 #define wqe_sr_WORD           word10
4398 #define wqe_ccpe_SHIFT        23
4399 #define wqe_ccpe_MASK         0x00000001
4400 #define wqe_ccpe_WORD         word10
4401 #define wqe_ccp_SHIFT         24
4402 #define wqe_ccp_MASK          0x000000ff
4403 #define wqe_ccp_WORD          word10
4404 	uint32_t word11;
4405 #define wqe_cmd_type_SHIFT    0
4406 #define wqe_cmd_type_MASK     0x0000000f
4407 #define wqe_cmd_type_WORD     word11
4408 #define wqe_els_id_SHIFT      4
4409 #define wqe_els_id_MASK       0x00000003
4410 #define wqe_els_id_WORD       word11
4411 #define LPFC_ELS_ID_FLOGI	3
4412 #define LPFC_ELS_ID_FDISC	2
4413 #define LPFC_ELS_ID_LOGO	1
4414 #define LPFC_ELS_ID_DEFAULT	0
4415 #define wqe_irsp_SHIFT        4
4416 #define wqe_irsp_MASK         0x00000001
4417 #define wqe_irsp_WORD         word11
4418 #define wqe_pbde_SHIFT        5
4419 #define wqe_pbde_MASK         0x00000001
4420 #define wqe_pbde_WORD         word11
4421 #define wqe_sup_SHIFT         6
4422 #define wqe_sup_MASK          0x00000001
4423 #define wqe_sup_WORD          word11
4424 #define wqe_wqec_SHIFT        7
4425 #define wqe_wqec_MASK         0x00000001
4426 #define wqe_wqec_WORD         word11
4427 #define wqe_irsplen_SHIFT     8
4428 #define wqe_irsplen_MASK      0x0000000f
4429 #define wqe_irsplen_WORD      word11
4430 #define wqe_cqid_SHIFT        16
4431 #define wqe_cqid_MASK         0x0000ffff
4432 #define wqe_cqid_WORD         word11
4433 #define LPFC_WQE_CQ_ID_DEFAULT	0xffff
4434 };
4435 
4436 struct wqe_did {
4437 	uint32_t word5;
4438 #define wqe_els_did_SHIFT         0
4439 #define wqe_els_did_MASK          0x00FFFFFF
4440 #define wqe_els_did_WORD          word5
4441 #define wqe_xmit_bls_pt_SHIFT         28
4442 #define wqe_xmit_bls_pt_MASK          0x00000003
4443 #define wqe_xmit_bls_pt_WORD          word5
4444 #define wqe_xmit_bls_ar_SHIFT         30
4445 #define wqe_xmit_bls_ar_MASK          0x00000001
4446 #define wqe_xmit_bls_ar_WORD          word5
4447 #define wqe_xmit_bls_xo_SHIFT         31
4448 #define wqe_xmit_bls_xo_MASK          0x00000001
4449 #define wqe_xmit_bls_xo_WORD          word5
4450 };
4451 
4452 struct lpfc_wqe_generic{
4453 	struct ulp_bde64 bde;
4454 	uint32_t word3;
4455 	uint32_t word4;
4456 	uint32_t word5;
4457 	struct wqe_common wqe_com;
4458 	uint32_t payload[4];
4459 };
4460 
4461 struct els_request64_wqe {
4462 	struct ulp_bde64 bde;
4463 	uint32_t payload_len;
4464 	uint32_t word4;
4465 #define els_req64_sid_SHIFT         0
4466 #define els_req64_sid_MASK          0x00FFFFFF
4467 #define els_req64_sid_WORD          word4
4468 #define els_req64_sp_SHIFT          24
4469 #define els_req64_sp_MASK           0x00000001
4470 #define els_req64_sp_WORD           word4
4471 #define els_req64_vf_SHIFT          25
4472 #define els_req64_vf_MASK           0x00000001
4473 #define els_req64_vf_WORD           word4
4474 	struct wqe_did	wqe_dest;
4475 	struct wqe_common wqe_com; /* words 6-11 */
4476 	uint32_t word12;
4477 #define els_req64_vfid_SHIFT        1
4478 #define els_req64_vfid_MASK         0x00000FFF
4479 #define els_req64_vfid_WORD         word12
4480 #define els_req64_pri_SHIFT         13
4481 #define els_req64_pri_MASK          0x00000007
4482 #define els_req64_pri_WORD          word12
4483 	uint32_t word13;
4484 #define els_req64_hopcnt_SHIFT      24
4485 #define els_req64_hopcnt_MASK       0x000000ff
4486 #define els_req64_hopcnt_WORD       word13
4487 	uint32_t word14;
4488 	uint32_t max_response_payload_len;
4489 };
4490 
4491 struct xmit_els_rsp64_wqe {
4492 	struct ulp_bde64 bde;
4493 	uint32_t response_payload_len;
4494 	uint32_t word4;
4495 #define els_rsp64_sid_SHIFT         0
4496 #define els_rsp64_sid_MASK          0x00FFFFFF
4497 #define els_rsp64_sid_WORD          word4
4498 #define els_rsp64_sp_SHIFT          24
4499 #define els_rsp64_sp_MASK           0x00000001
4500 #define els_rsp64_sp_WORD           word4
4501 	struct wqe_did wqe_dest;
4502 	struct wqe_common wqe_com; /* words 6-11 */
4503 	uint32_t word12;
4504 #define wqe_rsp_temp_rpi_SHIFT    0
4505 #define wqe_rsp_temp_rpi_MASK     0x0000FFFF
4506 #define wqe_rsp_temp_rpi_WORD     word12
4507 	uint32_t rsvd_13_15[3];
4508 };
4509 
4510 struct xmit_bls_rsp64_wqe {
4511 	uint32_t payload0;
4512 /* Payload0 for BA_ACC */
4513 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
4514 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
4515 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
4516 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
4517 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
4518 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
4519 /* Payload0 for BA_RJT */
4520 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
4521 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
4522 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
4523 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
4524 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
4525 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
4526 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
4527 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
4528 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
4529 	uint32_t word1;
4530 #define xmit_bls_rsp64_rxid_SHIFT  0
4531 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
4532 #define xmit_bls_rsp64_rxid_WORD   word1
4533 #define xmit_bls_rsp64_oxid_SHIFT  16
4534 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
4535 #define xmit_bls_rsp64_oxid_WORD   word1
4536 	uint32_t word2;
4537 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
4538 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
4539 #define xmit_bls_rsp64_seqcnthi_WORD   word2
4540 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
4541 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
4542 #define xmit_bls_rsp64_seqcntlo_WORD   word2
4543 	uint32_t rsrvd3;
4544 	uint32_t rsrvd4;
4545 	struct wqe_did	wqe_dest;
4546 	struct wqe_common wqe_com; /* words 6-11 */
4547 	uint32_t word12;
4548 #define xmit_bls_rsp64_temprpi_SHIFT  0
4549 #define xmit_bls_rsp64_temprpi_MASK   0x0000ffff
4550 #define xmit_bls_rsp64_temprpi_WORD   word12
4551 	uint32_t rsvd_13_15[3];
4552 };
4553 
4554 struct wqe_rctl_dfctl {
4555 	uint32_t word5;
4556 #define wqe_si_SHIFT 2
4557 #define wqe_si_MASK  0x000000001
4558 #define wqe_si_WORD  word5
4559 #define wqe_la_SHIFT 3
4560 #define wqe_la_MASK  0x000000001
4561 #define wqe_la_WORD  word5
4562 #define wqe_xo_SHIFT	6
4563 #define wqe_xo_MASK	0x000000001
4564 #define wqe_xo_WORD	word5
4565 #define wqe_ls_SHIFT 7
4566 #define wqe_ls_MASK  0x000000001
4567 #define wqe_ls_WORD  word5
4568 #define wqe_dfctl_SHIFT 8
4569 #define wqe_dfctl_MASK  0x0000000ff
4570 #define wqe_dfctl_WORD  word5
4571 #define wqe_type_SHIFT 16
4572 #define wqe_type_MASK  0x0000000ff
4573 #define wqe_type_WORD  word5
4574 #define wqe_rctl_SHIFT 24
4575 #define wqe_rctl_MASK  0x0000000ff
4576 #define wqe_rctl_WORD  word5
4577 };
4578 
4579 struct xmit_seq64_wqe {
4580 	struct ulp_bde64 bde;
4581 	uint32_t rsvd3;
4582 	uint32_t relative_offset;
4583 	struct wqe_rctl_dfctl wge_ctl;
4584 	struct wqe_common wqe_com; /* words 6-11 */
4585 	uint32_t xmit_len;
4586 	uint32_t rsvd_12_15[3];
4587 };
4588 struct xmit_bcast64_wqe {
4589 	struct ulp_bde64 bde;
4590 	uint32_t seq_payload_len;
4591 	uint32_t rsvd4;
4592 	struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4593 	struct wqe_common wqe_com;     /* words 6-11 */
4594 	uint32_t rsvd_12_15[4];
4595 };
4596 
4597 struct gen_req64_wqe {
4598 	struct ulp_bde64 bde;
4599 	uint32_t request_payload_len;
4600 	uint32_t relative_offset;
4601 	struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4602 	struct wqe_common wqe_com;     /* words 6-11 */
4603 	uint32_t rsvd_12_14[3];
4604 	uint32_t max_response_payload_len;
4605 };
4606 
4607 /* Define NVME PRLI request to fabric. NVME is a
4608  * fabric-only protocol.
4609  * Updated to red-lined v1.08 on Sept 16, 2016
4610  */
4611 struct lpfc_nvme_prli {
4612 	uint32_t word1;
4613 	/* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4614 #define prli_acc_rsp_code_SHIFT         8
4615 #define prli_acc_rsp_code_MASK          0x0000000f
4616 #define prli_acc_rsp_code_WORD          word1
4617 #define prli_estabImagePair_SHIFT       13
4618 #define prli_estabImagePair_MASK        0x00000001
4619 #define prli_estabImagePair_WORD        word1
4620 #define prli_type_code_ext_SHIFT        16
4621 #define prli_type_code_ext_MASK         0x000000ff
4622 #define prli_type_code_ext_WORD         word1
4623 #define prli_type_code_SHIFT            24
4624 #define prli_type_code_MASK             0x000000ff
4625 #define prli_type_code_WORD             word1
4626 	uint32_t word_rsvd2;
4627 	uint32_t word_rsvd3;
4628 
4629 	uint32_t word4;
4630 #define prli_fba_SHIFT                  0
4631 #define prli_fba_MASK                   0x00000001
4632 #define prli_fba_WORD                   word4
4633 #define prli_disc_SHIFT                 3
4634 #define prli_disc_MASK                  0x00000001
4635 #define prli_disc_WORD                  word4
4636 #define prli_tgt_SHIFT                  4
4637 #define prli_tgt_MASK                   0x00000001
4638 #define prli_tgt_WORD                   word4
4639 #define prli_init_SHIFT                 5
4640 #define prli_init_MASK                  0x00000001
4641 #define prli_init_WORD                  word4
4642 #define prli_conf_SHIFT                 7
4643 #define prli_conf_MASK                  0x00000001
4644 #define prli_conf_WORD                  word4
4645 #define prli_nsler_SHIFT		8
4646 #define prli_nsler_MASK			0x00000001
4647 #define prli_nsler_WORD			word4
4648 	uint32_t word5;
4649 #define prli_fb_sz_SHIFT                0
4650 #define prli_fb_sz_MASK                 0x0000ffff
4651 #define prli_fb_sz_WORD                 word5
4652 #define LPFC_NVMET_FB_SZ_MAX  65536   /* Driver target mode only. */
4653 };
4654 
4655 struct create_xri_wqe {
4656 	uint32_t rsrvd[5];           /* words 0-4 */
4657 	struct wqe_did	wqe_dest;  /* word 5 */
4658 	struct wqe_common wqe_com; /* words 6-11 */
4659 	uint32_t rsvd_12_15[4];         /* word 12-15 */
4660 };
4661 
4662 #define T_REQUEST_TAG 3
4663 #define T_XRI_TAG 1
4664 
4665 struct abort_cmd_wqe {
4666 	uint32_t rsrvd[3];
4667 	uint32_t word3;
4668 #define	abort_cmd_ia_SHIFT  0
4669 #define	abort_cmd_ia_MASK  0x000000001
4670 #define	abort_cmd_ia_WORD  word3
4671 #define	abort_cmd_criteria_SHIFT  8
4672 #define	abort_cmd_criteria_MASK  0x0000000ff
4673 #define	abort_cmd_criteria_WORD  word3
4674 	uint32_t rsrvd4;
4675 	uint32_t rsrvd5;
4676 	struct wqe_common wqe_com;     /* words 6-11 */
4677 	uint32_t rsvd_12_15[4];         /* word 12-15 */
4678 };
4679 
4680 struct fcp_iwrite64_wqe {
4681 	struct ulp_bde64 bde;
4682 	uint32_t word3;
4683 #define	cmd_buff_len_SHIFT  16
4684 #define	cmd_buff_len_MASK  0x00000ffff
4685 #define	cmd_buff_len_WORD  word3
4686 #define payload_offset_len_SHIFT 0
4687 #define payload_offset_len_MASK 0x0000ffff
4688 #define payload_offset_len_WORD word3
4689 	uint32_t total_xfer_len;
4690 	uint32_t initial_xfer_len;
4691 	struct wqe_common wqe_com;     /* words 6-11 */
4692 	uint32_t rsrvd12;
4693 	struct ulp_bde64 ph_bde;       /* words 13-15 */
4694 };
4695 
4696 struct fcp_iread64_wqe {
4697 	struct ulp_bde64 bde;
4698 	uint32_t word3;
4699 #define	cmd_buff_len_SHIFT  16
4700 #define	cmd_buff_len_MASK  0x00000ffff
4701 #define	cmd_buff_len_WORD  word3
4702 #define payload_offset_len_SHIFT 0
4703 #define payload_offset_len_MASK 0x0000ffff
4704 #define payload_offset_len_WORD word3
4705 	uint32_t total_xfer_len;       /* word 4 */
4706 	uint32_t rsrvd5;               /* word 5 */
4707 	struct wqe_common wqe_com;     /* words 6-11 */
4708 	uint32_t rsrvd12;
4709 	struct ulp_bde64 ph_bde;       /* words 13-15 */
4710 };
4711 
4712 struct fcp_icmnd64_wqe {
4713 	struct ulp_bde64 bde;          /* words 0-2 */
4714 	uint32_t word3;
4715 #define	cmd_buff_len_SHIFT  16
4716 #define	cmd_buff_len_MASK  0x00000ffff
4717 #define	cmd_buff_len_WORD  word3
4718 #define payload_offset_len_SHIFT 0
4719 #define payload_offset_len_MASK 0x0000ffff
4720 #define payload_offset_len_WORD word3
4721 	uint32_t rsrvd4;               /* word 4 */
4722 	uint32_t rsrvd5;               /* word 5 */
4723 	struct wqe_common wqe_com;     /* words 6-11 */
4724 	uint32_t rsvd_12_15[4];        /* word 12-15 */
4725 };
4726 
4727 struct fcp_trsp64_wqe {
4728 	struct ulp_bde64 bde;
4729 	uint32_t response_len;
4730 	uint32_t rsvd_4_5[2];
4731 	struct wqe_common wqe_com;      /* words 6-11 */
4732 	uint32_t rsvd_12_15[4];         /* word 12-15 */
4733 };
4734 
4735 struct fcp_tsend64_wqe {
4736 	struct ulp_bde64 bde;
4737 	uint32_t payload_offset_len;
4738 	uint32_t relative_offset;
4739 	uint32_t reserved;
4740 	struct wqe_common wqe_com;     /* words 6-11 */
4741 	uint32_t fcp_data_len;         /* word 12 */
4742 	uint32_t rsvd_13_15[3];        /* word 13-15 */
4743 };
4744 
4745 struct fcp_treceive64_wqe {
4746 	struct ulp_bde64 bde;
4747 	uint32_t payload_offset_len;
4748 	uint32_t relative_offset;
4749 	uint32_t reserved;
4750 	struct wqe_common wqe_com;     /* words 6-11 */
4751 	uint32_t fcp_data_len;         /* word 12 */
4752 	uint32_t rsvd_13_15[3];        /* word 13-15 */
4753 };
4754 #define TXRDY_PAYLOAD_LEN      12
4755 
4756 #define CMD_SEND_FRAME	0xE1
4757 
4758 struct send_frame_wqe {
4759 	struct ulp_bde64 bde;          /* words 0-2 */
4760 	uint32_t frame_len;            /* word 3 */
4761 	uint32_t fc_hdr_wd0;           /* word 4 */
4762 	uint32_t fc_hdr_wd1;           /* word 5 */
4763 	struct wqe_common wqe_com;     /* words 6-11 */
4764 	uint32_t fc_hdr_wd2;           /* word 12 */
4765 	uint32_t fc_hdr_wd3;           /* word 13 */
4766 	uint32_t fc_hdr_wd4;           /* word 14 */
4767 	uint32_t fc_hdr_wd5;           /* word 15 */
4768 };
4769 
4770 union lpfc_wqe {
4771 	uint32_t words[16];
4772 	struct lpfc_wqe_generic generic;
4773 	struct fcp_icmnd64_wqe fcp_icmd;
4774 	struct fcp_iread64_wqe fcp_iread;
4775 	struct fcp_iwrite64_wqe fcp_iwrite;
4776 	struct abort_cmd_wqe abort_cmd;
4777 	struct create_xri_wqe create_xri;
4778 	struct xmit_bcast64_wqe xmit_bcast64;
4779 	struct xmit_seq64_wqe xmit_sequence;
4780 	struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4781 	struct xmit_els_rsp64_wqe xmit_els_rsp;
4782 	struct els_request64_wqe els_req;
4783 	struct gen_req64_wqe gen_req;
4784 	struct fcp_trsp64_wqe fcp_trsp;
4785 	struct fcp_tsend64_wqe fcp_tsend;
4786 	struct fcp_treceive64_wqe fcp_treceive;
4787 	struct send_frame_wqe send_frame;
4788 };
4789 
4790 union lpfc_wqe128 {
4791 	uint32_t words[32];
4792 	struct lpfc_wqe_generic generic;
4793 	struct fcp_icmnd64_wqe fcp_icmd;
4794 	struct fcp_iread64_wqe fcp_iread;
4795 	struct fcp_iwrite64_wqe fcp_iwrite;
4796 	struct abort_cmd_wqe abort_cmd;
4797 	struct create_xri_wqe create_xri;
4798 	struct xmit_bcast64_wqe xmit_bcast64;
4799 	struct xmit_seq64_wqe xmit_sequence;
4800 	struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4801 	struct xmit_els_rsp64_wqe xmit_els_rsp;
4802 	struct els_request64_wqe els_req;
4803 	struct gen_req64_wqe gen_req;
4804 	struct fcp_trsp64_wqe fcp_trsp;
4805 	struct fcp_tsend64_wqe fcp_tsend;
4806 	struct fcp_treceive64_wqe fcp_treceive;
4807 	struct send_frame_wqe send_frame;
4808 };
4809 
4810 #define MAGIC_NUMER_G6 0xFEAA0003
4811 #define MAGIC_NUMER_G7 0xFEAA0005
4812 
4813 struct lpfc_grp_hdr {
4814 	uint32_t size;
4815 	uint32_t magic_number;
4816 	uint32_t word2;
4817 #define lpfc_grp_hdr_file_type_SHIFT	24
4818 #define lpfc_grp_hdr_file_type_MASK	0x000000FF
4819 #define lpfc_grp_hdr_file_type_WORD	word2
4820 #define lpfc_grp_hdr_id_SHIFT		16
4821 #define lpfc_grp_hdr_id_MASK		0x000000FF
4822 #define lpfc_grp_hdr_id_WORD		word2
4823 	uint8_t rev_name[128];
4824 	uint8_t date[12];
4825 	uint8_t revision[32];
4826 };
4827 
4828 /* Defines for WQE command type */
4829 #define FCP_COMMAND		0x0
4830 #define NVME_READ_CMD		0x0
4831 #define FCP_COMMAND_DATA_OUT	0x1
4832 #define NVME_WRITE_CMD		0x1
4833 #define FCP_COMMAND_TRECEIVE	0x2
4834 #define FCP_COMMAND_TRSP	0x3
4835 #define FCP_COMMAND_TSEND	0x7
4836 #define OTHER_COMMAND		0x8
4837 #define ELS_COMMAND_NON_FIP	0xC
4838 #define ELS_COMMAND_FIP		0xD
4839 
4840 #define LPFC_NVME_EMBED_CMD	0x0
4841 #define LPFC_NVME_EMBED_WRITE	0x1
4842 #define LPFC_NVME_EMBED_READ	0x2
4843 
4844 /* WQE Commands */
4845 #define CMD_ABORT_XRI_WQE       0x0F
4846 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4847 #define CMD_XMIT_BCAST64_WQE    0x84
4848 #define CMD_ELS_REQUEST64_WQE   0x8A
4849 #define CMD_XMIT_ELS_RSP64_WQE  0x95
4850 #define CMD_XMIT_BLS_RSP64_WQE  0x97
4851 #define CMD_FCP_IWRITE64_WQE    0x98
4852 #define CMD_FCP_IREAD64_WQE     0x9A
4853 #define CMD_FCP_ICMND64_WQE     0x9C
4854 #define CMD_FCP_TSEND64_WQE     0x9F
4855 #define CMD_FCP_TRECEIVE64_WQE  0xA1
4856 #define CMD_FCP_TRSP64_WQE      0xA3
4857 #define CMD_GEN_REQUEST64_WQE   0xC2
4858 
4859 #define CMD_WQE_MASK            0xff
4860 
4861 
4862 #define LPFC_FW_DUMP	1
4863 #define LPFC_FW_RESET	2
4864 #define LPFC_DV_RESET	3
4865